Motorola PowerQUICC II MPC8280 Series Reference Manual page 924

Freescale Semiconductor, Inc.
SMC in Transparent Mode
When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is
set, the SMC writes the message status bits into the BD and clears the R bit. It then starts
transmitting idles. When the end of the current BD is reached and the L bit is not set, only
R is cleared. In both cases, an interrupt is issued according to the I bit in the BD. By
appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a
specific buffer, or each block is sent. The SMC then proceeds to the next BD. If no
additional buffers have been presented to the SMC for transmission and the L bit was
cleared, an underrun is detected and the SMC begins sending idles.
If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer
on its next access. For instance, if a single TxBD is initialized with the CM and W bits set,
the buffer is sent continuously until R is cleared in the BD.
28.4.3 SMC Transparent Channel Reception Process
When the core enables the SMC receiver in transparent mode, it waits for synchronization
before receiving data. Once synchronization is achieved, the receiver transfers the incoming
data into memory according to the first RxBD in the table. Synchronization can be achieved
in two ways. First, when the receiver is connected to a TDM channel, it can be synchronized
to a time slot. Once the frame sync is received, the receiver waits for the first bit of its time
slot to occur before reception begins. Data is received only during the time slots defined by
the TSA. Secondly, when working with its own set of signals, the receiver starts reception
when SMSYNx is asserted.
When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I
bit in the BD is set. If incoming data exceeds the data buffer length, the SMC fetches the
next BD; if it is empty, the SMC continues transferring data to this BD's buffer. If the CM
bit is set in the RxBD, the E bit is not cleared, so the CP can automatically overwrite the
buffer on its next access.
28.4.4 Using SMSYN for Synchronization
The SMSYN signal offers a way to externally synchronize the SMC channel. This method
differs somewhat from the synchronization options available in the SCCs and should be
studied carefully. See Figure 28-11 for an example.
Once SMCMR[REN] is set, the first rising edge of SMCLK that finds SMSYN low causes
the SMC receiver to achieve synchronization. Data starts being received or latched on the
same rising edge of SMCLK that latched SMSYN. This is the first bit of data received. The
receiver does not lose synchronization again, regardless of the state of SMSYN, until REN
is cleared.
Once SMCMR[TEN] is set, the first rising edge of SMCLK that finds SMSYN low
synchronizes the SMC transmitter which begins sending ones asynchronously from the
falling edge of SMSYN. After one character of ones is sent, if the transmit FIFO is loaded
28-24 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
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