Motorola PowerQUICC II MPC8280 Series Reference Manual page 1018

Features
— Asymmetric cell size for send and receive
— HEC octet insertion option
• PHY
— UTOPIA level II supports 8/16 bits 25/50 MHz
– Supports UTOPIA master and slave modes
– Supports cell-level handshake
– Supports multiple-PHY polling mode
• ATM pace control (APC) unit
— Peak cell rate pacing on a per-VC basis
— Peak-and-sustain cell rate pacing using GCRA on a per-VC basis
— Peak-and-minimum cell rate pacing on a per-VC basis
— Up to eight priority levels
— Fully managed by CP with no host intervention
• Available bit rate (ABR)
— Performs ATMF UNI 4.0 ABR flow control on a per-VC basis
— Automatic forward-RM, backward-RM cells generation
— Automatic feedback rate adaptation
— Support for EFCI (explicit forward congestion indication) and ER (explicit rate)
— RM cell floating-point calculations
— Fully managed by CP with no host intervention
• Receive address look-up mechanism
— Two modes of address look-up are supported
– External CAM
– Address compression
• OAM (operations and maintenance) cells
— OAM filtering according to PTI field and reserved VCI field
— Raw cell queues for transmission and reception
— CRC-10 generation/check
— Performance monitoring support
– Support up to 64 bidirectional block tests simultaneously
– Automatic FMC and BRC cell generation and termination
– User transmit cell
– User transmit cell
– PM cells time stamp insertion
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MPC8280 PowerQUICC II Family Reference Manual
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