Motorola PowerQUICC II MPC8280 Series Reference Manual page 1294

TC Layer Programming Mode
35.4 TC Layer Programming Mode
This section describes the TC layer-specific registers and other programming model
features. For a complete and concise list of TC layer registers, refer to Chapter 3, "Memory
Map."
35.4.1 TC Layer Registers
Each TC layer block is controlled by registers located in the block and accessed from the
60x bus.
35.4.1.1 TC Layer Mode Registers 1–8 (TCMODEx)
Each TC layer block is configured using a TC layer mode register TCMODEx, as shown in
Figure 35-5.
0 1 2
Field RXEN TXEN RPS TPS
Reset
R/W
Figure 35-5. TC Layer Mode Registers (TCMODEx)
Table 35-2 describes TCMODE fields.
Bits Name
0 RXEN TC Layer Rx enable bit. Enables the TC Layer Rx block operation:
0 TC Layer Rx operation is disabled.
1 TC Layer Rx operation is enabled.
1 TXEN TC Layer Tx enable bit. Enables the TC Layer Tx block operation:
0 TC Layer Tx operation is disabled.
1 TC Layer Tx operation is enabled.
2 RPS Rx Payload DeScrambling
0 Payload descrambling is performed on received payload data.
1 No payload descrambling is performed on received payload data.
3 TPS Tx Payload Scrambling
0 Payload scrambling is performed on transmitted payload data.
1 No payload scrambling is performed on transmitted payload data.
4 RC Rx Coset Enable
0 XOR with 0xAA is done on received HEC.
1 No XOR with 0xAA is done on received HEC.
5 TC Tx Coset Enable
0 XOR with 0xAA is done on transmitted HEC.
1 No XOR with 0xAA is done on transmitted HEC.
35-8
Freescale Semiconductor, Inc.
3 4 5 6
RC TC SBC
0000_0000_0000_0000
Table 35-2. TCMODEx Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
7 8 9 10 11
CF URE LB
R/W
Description
12 13 14 15
TBA IMA SM CM
MOTOROLA