Motorola PowerQUICC II MPC8280 Series Reference Manual page 1194

AAL2 Receiver
Table 33-6 describes the AAL2 RCT fields.
Table 33-6. AAL2 Protocol-Specific RCT Field Descriptions
Offset Bits Name
0x00 0–1 —
2 GBL
3–4 BO
5 —
6 DTB
7 BIB
8-9 —
10 SEGF
11 ENDF
12 —
13 MAP
14-15 INTQ
0x02 0–11 —
12 NoSTF
13–15 AAL
33-26
Freescale Semiconductor, Inc.
1
Reserved, should be cleared during initialization.
Global. Setting GBL enables snooping of data buffers, BDs, interrupt queues and free
buffer pool.
Byte ordering—used for data buffers.
00 Reserved
01 munged little endian
1x Big endian
Reserved, should be cleared during initialization.
Data buffer bus selection.
0 Reside on the 60x bus.
1 Reside on the local bus.
Bus selection for the BDs, interrupt queues, CID mapping table, RxQDs, and the free
buffer pool.
0 Reside on the 60x bus.
1 Reside on the local bus.
Reserved, should be cleared during initialization.
OAM F5 segment filtering
0 Do not send cells with PTI=100 to the raw cell queue.
1 Send cells with PTI=100 to the raw cell queue.
OAM F5 end-to-end filtering
0 Do not send cells with PTI=101 to the raw cell queue.
1 Send cells with PTI=101 to the raw cell queue.
Reserved, should be cleared during initialization.
CID mapping table memory location select
0 Resides in the dual-port RAM.
1 Resides in external memory.
Assigns one of the four available interrupt queues to this ATM channel number.
Reserved, should be cleared during initialization.
No STF byte.
0 Normal AAL2 cell structure.
1 The cell does not include the STF byte. In this mode each cell starts with a packet
and contains only whole packets (no split or part).
AAL type
000 AAL0 —Reassembly with no adaptation layer
001 AAL1 —ATM adaptation layer 1 protocol
010 AAL5 —ATM adaptation layer 5 protocol
100 AAL2 —ATM adaptation layer 2 protocol
101 AAL1_CES. Refer to Chapter 32, "ATM AAL1 Circuit Emulation Service."
All others reserved.
MPC8280 PowerQUICC II Family Reference Manual
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