Motorola PowerQUICC II MPC8280 Series Reference Manual page 1401

41.4.1 General Purpose I/O Pins
Each one of the port pins is independently configured as a general-purpose I/O pin if the
corresponding port pin assignment register (PPAR) bit is cleared. Each pin is configured as
a dedicated on-chip peripheral pin if the corresponding PPAR bit is set.When the port pin
is configured as a general-purpose I/O pin, the signal direction for that pin is determined by
the corresponding control bit in the port data direction register (PDIR). The port I/O pin is
configured as an input if the corresponding PDIR bit is cleared; it is configured as an output
if the corresponding PDIR bit is set. All PPAR and PDIR bits are cleared on total system
reset, configuring all port pins as general-purpose input pins.
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port
data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin
is configured as an output, the output latch data is gated onto the port pin. In this case, when
PDATx is read, the port pin itself is read. If a port pin is configured as an input, data written
to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In
this case, when PDATx is read, the state of the port pin is read.
41.4.2 Dedicated Pins
When a port pin is not configured as a general-purpose I/O pin, it has a dedicated
functionality, as described in the following tables. Note that if an input to a peripheral is not
supplied from a pin, a default value is supplied to the on-chip peripheral as listed in the
right-most column.
Some output functions can be output on 2 different pins. For
example, the output for BRG1 can come out on both PC31 and
PD19. The user can freely configure such functions to be
output on two pins at once. However, there is typically no
advantage in doing so unless there is a large fanout where it is
advantageous to share the load between two pins.
Many input functions can also come from two different pins;
see Section 41.5, "Ports Tables."
41.5 Ports Tables
Table 41-5 through Table 41-8 describe the ports functionality according to the
configuration of the port registers (PPARx, PSORx, and PDIRx). Each pin can function as
a general purpose I/O, one of two dedicated outputs, or one of two dedicated inputs.
As shown in Figure 41-7, some input functions can come from two different pins for
flexibility. Secondary option programming is relevant only if primary option is
programmed to the default value.
MOTOROLA
Freescale Semiconductor, Inc.
NOTE
Chapter 41. Parallel I/O Ports
For More Information On This Product,
Go to: www.freescale.com
Ports Tables
41-7