Motorola PowerQUICC II MPC8280 Series Reference Manual page 949

0
Field —
Reset
R/W
Addr
Figure 29-5. Rx Internal State (RSTATE) High Byte
RSTATE high-byte fields are described in Table 29-5.
Table 29-5. RSTATE High-Byte Field Descriptions
Bits Name
0–1 — Reserved, should be cleared.
2 GBL Global. Setting GBL activates snooping (only the 60x bus can be snooped, this parameter is ignored
for local bus transactions).
3–4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame or at the beginning of the next BD.
00 Reserved
01 Munged little-endian.
1x Big-endian
5 TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6 DTB Data bus indicator.
The transfers to data buffers are handled by the:
0 60x bus SDMA
1 Local bus SDMA
7 BDB BD and interrupt circular tables bus indicator.
The transfers to/from BD and interrupt circular tables are handled by the:
0 60x bus SDMA
1 Local bus SDMA
Note: The following restrictions result from the fact that there is a common bus selection bit for BDs
and interrupt circular tables:
• The RxBDs of all the channels that use a particular interrupt table must reside on the same bus
(60x or local).
• All TxBDs must reside on the same bus (60x or local).
29.3.2 Channel-Specific Transparent Parameters
Table 29-6 describes channel-specific parameters for transparent operation.
MOTOROLA
Freescale Semiconductor, Inc.
1 2 3
GBL
Chapter 29. Multi-Channel Controllers (MCCs)
For More Information On This Product,
Go to: www.freescale.com
Channel-Specific Parameters
4 5
BO TC2
—
R/W
0x20
Description
6 7
DTB BDB
29-11