Motorola PowerQUICC II MPC8280 Series Reference Manual page 1122

Features
– AAL1 misinserted cell count
– AAL1 pointer mismatch/parity error
– AAL1 Rx buffer pre-overflow
— Segmentation
– Segment PDU directly from external memory
– Partially filled cells support (configurable on a per-VC basis)
– Sequence number generation
– Sequence number protection (CRC-3 and even parity) generation
– Pointer generation during segmentation in structure AAL1 cell format
– Clock recovery using external SRTS logic during reassembly in unstructured
AAL1
– Statistics gathering on a per-VC basis:
– AAL1 Tx cell count
– AAL1 Tx buffer underrun
• Circuit emulation service (CES)
— ATM to TDM
– Structured and unstructured data are transferred between the ATM and MCC
automatically without CPU intervention
– In case of pre-underrun, the MCC start sending the last frame or the
user-defined underrun template. The MCC and ATM controller automatically
perform slip control with no CPU intervention.
– In case of pre-overrun, the ATM receiver discards incoming cells until the
MCC transmitter empties enough buffers for the receiver to restart.
– Supports common channel signaling (CCS)
– Supports channel associated signaling (CAS)
– Up to 4 (one per trunk) CAS blocks residing in internal RAM when in
automatic CAS mode and up to 8 blocks when in core CAS modify mode
– Supports Nx64 E1/T1 channels
– CAS routing table on per-VC basis
– Automatic un-packing of the CAS information during reassembly and
updating of the internal CAS block
— TDM to ATM
– Structured and unstructured data are automatically transferred between the
MCC and ATM controller without CPU intervention
– Supports common channel signaling (CCS)
– Supports channel associated signaling (CAS)
– Up to 4 (one per trunk) CAS blocks residing in internal RAM when in
32-2
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MPC8280 PowerQUICC II Family Reference Manual
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