Motorola PowerQUICC II MPC8280 Series Reference Manual page 1110

Transmission Rate Modes—External, Internal, and Expanded Internal
Table 31-49 describes COMM_INFO fields.
Table 31-49. COMM_INFO Field Descriptions
Offset Bits Name
0x86 0–4 — Reserved, should be cleared.
5 CTB Connection tables bus. Used for external channels only
0 External connection tables reside on the 60x bus.
1 External connection tables reside on the local bus.
6–10 PHY# PHY number. In single PHY mode this field should be cleared In multiple PHY mode this
field is an index to the APC parameter table associated with this channel.
11–12 ACT ATM channel type
00 Other channel
01 VBR channel
1x Reserved
13-15 PRI APC priority level.
000 Highest priority (APC_LEVEL1)
111 Lowest priority (APC_LEVEL8).
0x88 0-15 CC Channel code. The channel code associated with the current channel.
0x8A 0-15 BT Burst tolerance. For use by VBR channels only (ACT field is 0b01). Specifies the initial burst
tolerance (GCRA burst credit) of the current VC.
31.15 Transmission Rate Modes—External, Internal,
and Expanded Internal
The ATM controller supports the following three rate modes:
• External rate mode—The total transmission rate is determined by the PHY
transmission rate. The FCC sends cells to keep the PHY FIFOs full; the FCC inserts
idle/unassign cells to maintain the transmission rate.
• Internal rate mode—The total transmission rate is determined by the FCC internal
rate timers. In this mode, the FCC does not insert idle/unassign cells. The internal
rate mechanism is supported for the first four PHY devices (PHY address 0-3). Each
PHY has its own FTIRR, described in Section 31.15.1.1, "FCC Transmit Internal
Rate Register (FTIRRx)." The FTIRR includes the initial value of the internal rate
timer. A cell transmit request is sent when an internal rate timer expires. When using
internal rate mode, the user assigns one of the baud-rate generators (BRGs) to clock
the four internal rate timers.
• Internal rate expanded mode—The total transmission rate is determined by the FCC
internal rate timers and by the assignment of rate per PHY. In this mode, the FCC
does not insert idle/unassign cells. The internal rate expanded mode differs from the
internal rate mode in that the internal rate mechanism is extended for 31 PHY
devices (PHY addresses 0-30) and there cannot be a mix of external and internal rate
PHYs. Expanded internal rate is configured by registers GFEMRx, FIRPERx,
31-96
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
MOTOROLA