Motorola PowerQUICC II MPC8280 Series Reference Manual page 1016

Features
• Bridges and routers with ATM interface
31.1 Features
The ATM controller has the following features:
• Full duplex segmentation and reassembly at 155 Mbps
• UTOPIA level II master and slave modes 8/16 bit
• AAL5, AAL1, AAL2, AAL0 protocols
• Up to 255 active VCs internally, and up to 64K VCs using external memory
• TM 4.0 CBR, VBR, UBR, UBR+ traffic types
• VBR type 1 and 2 traffic using leaky buckets (GCRA)
• TM 4.0 ABR flow control (EFCI and ER)
• Idle/unassign cells screening/transmission option
• External and internal rate transmit modes
• Special mode for ATM-to-TDM or ATM-to-ATM data forwarding
• CLP and congestion indication marking
• User-defined cells up to 65 bytes
• Separate TxBD and RxBD tables for each virtual channel (VC)
• Special mode of global free buffer pools for dynamic and efficient memory
allocation with early packet discard (EPD) support
• Interrupt report per channel using four priority interrupt queues
• Compliant with ATMF UNI 4.0 and ITU specification
• AAL5 cell format
— Reassembly
– Reassemble PDU directly to external memory
– CRC32 check
– CLP and congestion report
– CPCS_UU, CPI, and length check
– Abort message report
— Segmentation
– Segment PDU directly from external memory
– Performs PDU padding
– CRC32 generation
– Automatic last cell marking
– Automatic CPCS_UU, CPI, and length insertion
31-2
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA