Motorola PowerQUICC II MPC8280 Series Reference Manual page 1371

Table 39-5. SPI Parameter RAM Memory Map (continued)
1
Offset Name Width
0x1C — Word The Tx internal data pointer
0x20 TBPTR Hword TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be
0x22 — Hword The Tx internal byte count
0x24 — Word Tx temp.
0x34 — Word SDMA temp.
1
From the pointer value programmed in SPI_BASE at IMMR + 0x89FC.
2
Normally, these parameters need not be accessed. They are listed to help experienced users in debugging.
39.5.1 Receive/Transmit Function Code Registers
(RFCR/TFCR)
Figure 39-9 shows the fields in the receive/transmit function code registers (RFCR/TFCR).
0
Field —
Reset
R/W
Addr
Figure 39-9. RFCR/TFCR—Function Code Registers
Table 39-6 describes the RFCR/TFCR fields.
Bits Name
0–1 — Reserved, should be cleared.
2 GBL Global access bit
0 Disable memory snooping
1 Enable memory snooping
3–4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame or BD.
00 True little-endian. Note this mode can only be used with 32-bit port size memory.
01 Big-endian
1x Munged little-endian
5 TC2 Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
MOTOROLA
Freescale Semiconductor, Inc.
in the buffer to be accessed.
processed when idle. After reset or when the end of the Tx BD table is reached, the CP
initializes TBPTR to the TBASE value. Most applications do not need to modify TBPTR,
but it can be updated when the transmitter is disabled or when no Tx buffer is in use.
2
decremented with every byte read by the SDMA channels.
2
Reserved for CP use.
1 2 3
GBL
SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR)
Table 39-6. RFCR/TFCR Field Descriptions
Chapter 39. Serial Peripheral Interface (SPI)
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Description
2
is updated by the SDMA channels to show the next address
is a down-count value initialized with TxBD[Data Length] and
4 5
BO TC2
0000_0000
R/W
Description
SPI Parameter RAM
6 7
DTB —
39-13