Motorola PowerQUICC II MPC8280 Series Reference Manual page 796

SCC BISYNC Parameter RAM
Table 23-1. SCC BISYNC Parameter RAM Memory Map
1
Offset Name
0x30 —
0x34 CRCC
0x38 PRCRC
0x3A PTCRC
0x3C PAREC
0x3E BSYNC
0x40 BDLE
0x42 CHARACTER1 Hword Control character 1–8. These values represent control characters that the
0x44 CHARACTER2 Hword
0x46 CHARACTER3 Hword
0x48 CHARACTER4 Hword
0x4A CHARACTER5 Hword
0x4C CHARACTER6 Hword
0x4E CHARACTER7 Hword
0x50 CHARACTER8 Hword
0x52 RCCM
1
From SCCx base address. See Section 20.3.1, "SCC Base Addresses."
GSMR[MODE] determines the protocol for each SCC. The SYN1–SYN2 synchronization
characters are programmed in the DSR (see Section 20.1.3, "Data Synchronization Register
(DSR).") The BISYNC controller uses the same basic data structure as other modes;
receive and transmit errors are reported through their respective BDs. There are two basic
ways to handle BISYNC channels:
• The controller inspects the data on a per-byte basis and interrupts the core each time
a byte is received.
• The controller can be programmed so software handles the first two or three bytes.
The controller directly handles subsequent data without interrupting the core.
23-4
Freescale Semiconductor, Inc.
Width
Word Reserved
Word CRC constant temp value.
Hword Preset receiver/transmitter CRC16/LRC. These values should be preset to all
ones or zeros, depending on the BCS used.
Hword
Hword Receive parity error counter. This 16-bit (modulo 2
CP counts parity errors on receive if the parity feature of BISYNC is enabled.
Initialize PAREC while the channel is disabled.
Hword BISYNC SYNC register. Contains the value of the SYNC to be sent as the second
byte of a DLE–SYNC pair in an underrun condition and stripped from incoming
data on receive once the receiver synchronizes to the data using the DSR and
SYN1–SYN2 pair. See Section 23.7, "BISYNC SYNC Register (BSYNC)."
Hword BISYNC DLE register. Contains the value to be sent as the first byte of a
DLE–SYNC pair and stripped on receive. See Section 23.8, "SCC BISYNC DLE
Register (BDLE)."
BISYNC controller recognizes. See Section 23.6, "SCC BISYNC Control
Character Recognition."
Hword Receive control character mask. Masks CHARACTERn comparison so control
character classes can be defined. Setting a bit enables and clearing a bit masks
comparison. See Section 23.6, "SCC BISYNC Control Character Recognition."
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Description
16
) counter maintained by the
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