Motorola PowerQUICC II MPC8280 Series Reference Manual page 506

User-Programmable Machines (UPMs)
Internal/external
memory access request
UPM refresh
timer request
command
RUN
(issued in software)
Exception request
Request
UPMWAIT
Logic
Figure 11-55. User-Programmable Machine Block Diagram
The RAM array contains 64 32-bit RAM words. The signal timing generator loads the
RAM word from the RAM array to drive the general-purpose lines, byte-selects, and
chip-selects. If the UPM reads a RAM word with WAEN set, the external UPMWAIT
signal is sampled and synchronized by the memory controller and the current request is
frozen.
When a new access to external memory is requested by any device on the 60x or local bus,
the addresses of the transfer are compared to each one of the valid banks defined in the
memory controller. When an address match is found in one of the memory banks, BRx[MS]
selects the UPM to handle this memory access. MxMR[BSEL] assigns the UPM to the 60x
or the local bus.
Note that 60x bus accesses that hit a bank allocated to the local bus are transferred to the
local bus. However, local bus accesses that hit a bank allocated to the 60x bus are ignored.
11.6.1 Requests
An internal or external device's request for a memory access initiates one of the following
patterns (MxMR[OP] = 00):
• Read single-beat pattern (RSS)
• Read burst cycle pattern (RBS)
• Write single-beat pattern (WSS)
• Write burst cycle pattern (WBS)
These patterns are described in Section 11.6.1.1, "Memory Access Requests."
11-68
Freescale Semiconductor, Inc.
Array
Index
Generator
Increment
Index
Wait
Hold (LAST = 0)
WAEN Bit
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Index
RAM Array
Internal Signals
Signals Timing
Latch Generator
Internal Controls
GPLx, BS_x, CSx
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