Motorola PowerQUICC II MPC8280 Series Reference Manual page 479

• Precharge to activate interval (P/LSDMR[PRETOACT]). See Section 11.4.6.1,
"Precharge-to-Activate Interval."
• Activate to read/write interval (P/LSDMR[ACTTORW]). See Section 11.4.6.2,
"Activate to Read/Write Interval."
• CAS latency, column address to first data out (P/LSDMR[CL]). See
Section 11.4.6.3, "Column Address to First Data Out—CAS Latency."
• Last data out to precharge (P/LSDMR[LDOTOPRE]). Section 11.4.6.4, "Last Data
Out to Precharge."
• Write recovery, last data in to precharge (P/LSDMR[WRC]). See Section 11.4.6.5,
"Last Data In to Precharge—Write Recovery."
• Refresh recovery interval (P/LSDMR[RFRC]). See Section 11.4.6.6, "Refresh
Recovery Interval (RFRC)."
• External address multiplexing present (P/LSDMR[EAMUX]). See Section 11.4.6.7,
"External Address Multiplexing Signal."
• External buffers on the control lines present (P/LSDMR[BUFCMD]). See
Section 11.4.6.8, "External Address and Command Buffers (BUFCMD)."
The following sections describe the SDRAM parameters that are programmed in the
P/LSDMR register.
11.4.6.1 Precharge-to-Activate Interval
As demonstrated in Figure 11-20, this parameter, controlled by P/LSDMR[PRETOACT]
defines the earliest timing for activate or refresh command after a precharge command.
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Chapter 11. Memory Controller
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SDRAM Machine
11-41