Motorola PowerQUICC II MPC8280 Series Reference Manual page 538

Memory System Interface Example Using UPM
CLKIN
A
Row
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1 0
cst2 0
cst3 0
cst4 0
bst1 1
bst2 1
bst3 1
bst4 1
g0l0
g0l1
g0h0
g0h1
g1t1 1
g1t3 1
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop 0
exen 0
amx0 1
amx1 0
na 0
uta 0
todt 0
last 0
WSS
Figure 11-78. Single-Beat Write Access to EDO DRAM
11-100
Freescale Semiconductor, Inc.
Column 1
0 0 1
0 0 1
0 1 1
0 1 1
1 0 0
0 0 0
0 0 0
0 0 1
1 1 1
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
WSS+1 WSS+2 WSS+3
MPC8280 PowerQUICC II Family Reference Manual
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Bit 0
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