Motorola PowerQUICC II MPC8280 Series Reference Manual page 557

• BCR[L2C] = 1—L2 cache is present.
• BCR[L2D] = 0—L2 response time. In this case, the L2 will claim a bus transaction
one clock cycle after TS assertion.
• BCR[APD] = 1: This parameter is not L2 specific, but should consider the L2
ARTRY assertion timing.
See Section 4.3.2.1, "Bus Configuration Register (BCR)," for more details about these
parameters.
12.3 System Requirements When Using the L2 Cache
Interface
The following requirements apply to MPC8280-based systems that implement an external
L2 cache:
• For systems that use copy-back mode, all cachable memory regions must be marked
as global in the CPU's MMU and the CPM. This causes the assertion of the GBL
signal on every cachable transaction. Systems that use write-through mode (or
ECC/Parity mode) have no such restriction.
• All cachable memory regions must have a 64-bit port size.
• All cachable memory regions must not set the BRx[DR] bit.
• All cachable memory regions must not use ECC or parity unless the external L2 is
connected as described in Section 12.1.3, "ECC/Parity Mode."
• All non-cachable memory regions must be marked as caching-inhibited in the
CPU's MMU. This causes the assertion of the CI signal on every non-cachable
transaction. Note that the MPC8280's internal space (IMMR) and any memory
banks assigned to the local bus are always considered non-cachable.
12.4 L2 Cache Operation
When configured for an L2 cache (BCR[L2C] = 1), the MPC8280 samples the L2_HIT
input signal when the delay time programmed in BCR[L2D] expires. For 60x bus cycles, if
L2_HIT is asserted, the external L2 cache drives AACK and TA to complete the transaction
without the MPC8280 initiating a system memory transfer.
The external L2 cache can assert ARTRY to retry 60x bus cycles, and can request the bus
by asserting BR to perform L2 cast-out operations. The arbiter grants the address and data
bus to the external L2 cache by asserting BG and DBG, respectively. If the external L2
cache asserts ARTRY, it should not assert L2_HIT.
For more information about the timing and behavior of the MPC2605 integrated L2 cache,
refer to the MPC2605 data sheet.
MOTOROLA
Freescale Semiconductor, Inc.
System Requirements When Using the L2 Cache Interface
Chapter 12. Secondary (L2) Cache Support
For More Information On This Product,
Go to: www.freescale.com
12-7