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Motorola MC68306 User Manual

Integrated ec000 processor
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MC68306
Integrated EC000 Processor
User's Manual
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© MOTOROLA, 1993

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  Summary of Contents for Motorola MC68306

  • Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
  • Page 2 The MC68306 EC000 Integrated Processor User’s Manual describes the programming, capabilities, registers, and operation of the MC68306; the MC68000 Family Programmer’s Reference Manual provides instruction details for the MC68306; and the MC68306 EC000 Integrated Processor Product Brief provides a brief description of the MC68306 capabilities.
  • Page 3 — Sales Offices — UNITED STATES FINLAND, Helsinki 358-0-35161191 Car Phone 358(49)211501 ALABAMA, Huntsville (205) 464-6800 FRANCE, Paris/Vanves 33(1)40 955 900 ARIZONA, Tempe (602) 897-5056 GERMANY , Langenhagen/ Hanover 49(511)789911 CALIFORNIA, Agoura Hills (818) 706-1929 GERMANY , Munich 49 89 92103-0 CALIFORNIA, Los Angeles (310) 417-8848 GERMANY , Nuremberg...
  • Page 4: Table Of Contents

    2.1.13 Upper And Lower Data Strobes (UDS , LDS ) ............. 2-7 2.1.14 Upper Byte Write (UW ) ..................2-8 2.1.15 Lower Byte Write (LW )..................2-8 2.1.16 Output Enable (OE) ................... 2-8 2.1.17 Reset (RESET ) ....................2-8 2.2 Chip Select Signals....................2-9 MOTOROLA MC68306 USER'S MANUAL...
  • Page 5 2.7.5 Test Reset (TRST) ....................2-12 Section 3 68000 Bus Operation Description 3.1 Data Transfer Operations ..................3-1 3.1.1 Read Cycle ......................3-1 3.1.2 Write Cycle ......................3-4 3.1.3 Read-Modify-Write Cycle..................3-7 3.1.4 CPU Space Cycle ....................3-11 MC68306 USER'S MANUAL MOTOROLA...
  • Page 6 4.6.4 Spurious Interrupt Exception................4-18 4.6.5 Instruction Traps ....................4-18 4.6.6 Illegal and Unimplemented Instructions ............... 4-18 4.6.7 Privilege Violations....................4-19 4.6.8 Tracing ......................... 4-19 4.6.9 Bus Error ......................4-20 4.6.10 Address Error ..................... 4-21 4.6.11 Multiple Exceptions .................... 4-21 MOTOROLA MC68306 USER'S MANUAL...
  • Page 7 Number Title Number Section 5 System Operation 5.1 MC68306 Address Space ..................5-1 5.2 Register Description ....................5-3 5.2.1 System Register ....................5-3 5.2.2 Timer Vector Register ..................5-4 5.2.3 Bus Timeout Period Register................5-4 5.2.4 Interrupt Registers ....................5-5 5.2.4.1 Interrupt Control Register .................
  • Page 8 6.4.1.10 Interrupt Status Register (DUISR) ..............6-31 6.4.1.11 Interrupt MASK Register (DUIMR)..............6-33 6.4.1.12 Count Register Current MSB of Counter (DUCUR) ........6-33 6.4.1.13 Count Register Current LSB of Counter (DUCLR) ......... 6-33 6.4.1.14 Counter/Timer Upper Preload Register (CTUR) ..........6-34 MOTOROLA MC68306 USER'S MANUAL...
  • Page 9 7.4.1 EXTEST (000) ..................... 7-10 7.4.2 SAMPLE/PRELOAD (110) .................. 7-10 7.4.3 BYPASS (010, 101, 111) ..................7-11 7.4.4 CLAMP (011) ...................... 7-11 7.5 MC68306 Restrictions .................... 7-11 7.6 Non-IEEE 1149.1 Operation ................... 7-12 Section 8 Electrical Specifications 8.1 Maximum Ratings ....................8-1 8.2 Thermal Characteristics ..................
  • Page 10 8.15 AC Electrical Characteristics—Transmitter Timing ..........8-17 8.16 AC Electrical Characteristics—Receiver Timing ........... 8-18 8.17 IEEE 1149.1 Electrical Characteristics ..............8-19 Section 9 Ordering Information and Mechanical Data 9.1 Standard Ordering Information ................9-1 9.2 Pin Assignments ..................... 9-2 MOTOROLA MC68306 USER'S MANUAL...
  • Page 11 Title Number Figure 1-1. MC68306 Simplified Block Diagram............1-1 Figure 2-1. MC68306 Detailed Block Diagram ............2-2 Figure 3-1. Word Read Cycle Flowchart ..............3-2 Figure 3-2. Byte Read Cycle Flowchart ..............3-2 Figure 3-3. Read and Write Cycle Timing Diagram ..........3-3 Figure 3-4.
  • Page 12 Figure 8-7. Bus Arbitration Timing Diagram ............. 8-11 Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh ..........8-13 Figure 8-9. DRAM Timing – 1-Wait Write, No Refresh ..........8-14 Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh ..........8-14 MOTOROLA MC68306 USER'S MANUAL xiii...
  • Page 13 Figure 8-15. Transmit Timing ................... 8-17 Figure 8-16. Receive Timing ..................8-18 Figure 8-17. Test Clock Input Timing Diagram ............8-19 Figure 8-18. Boundary Scan Timing Diagram ............8-20 Figure 8-19. Test Access Port Timing Diagram ............8-20 MC68306 USER'S MANUAL MOTOROLA...
  • Page 14 Table 4-4. EC000 Core Instruction Set Summary ............ 4-8 Table 4-5. Exception Vector Assignments ..............4-16 Table 4-6. Exception Grouping and Priority .............. 4-22 Table 5-1. MC68306 Memory Map ................5-2 Table 5-2. Chip Select Match Bits ................5-11 Table 5-3. DRAM Address Multiplexer..............5-13 Table 5-4.
  • Page 15 LIST OF TABLES (Continued) Table Page Number Title Number Table 7-1. Boundary Scan Control Bits ..............7-4 Table 7-2. Boundary Scan Bit Definitions ..............7-5 Table 7-3. Instructions ....................7-10 MC68306 USER'S MANUAL MOTOROLA...
  • Page 16: Introduction

    MC68000-class performance will find that the MC68306 reduces design time by providing valuable system elements integrated in one chip. The combination of peripherals offered in the MC68306 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing.
  • Page 17: Mc68Ec000 Core Processor

    The primary features of the MC68306 are as follows: • Functional Integration on a Single Piece of Silicon • EC000 Core—Identical to MC68EC000 Microprocessor — Complete Code Compatibility with MC68000 and MC68EC000 — High Performance—2.4 MIPS — Extended Internal Address Range – to 4 Gbyte •...
  • Page 18: On-Chip Peripherals

    To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. The functions on the MC68306 include two serial channels, a timer/counter, a DRAM controller, a parallel port, and system glue logic.
  • Page 19: Chip Selects

    1.2.6 Clock To save on system costs, the MC68306 has an on-board oscillator that can be driven with a 16.67-MHz crystal. A bus clock output is provided by a CLKOUT pin. Alternatively, an MC68306 USER'S MANUAL...
  • Page 20: Bus Timeout Monitor

    4096 clocks. 1.2.8 IEEE 1149.1 Test To aid in system diagnostics, the MC68306 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group).
  • Page 21: Signal Descriptions

    The term negate or negation is used to indicate that a signal is inactive or false. MOTOROLA MC68306 USER'S MANUAL 2- 1...
  • Page 22: Figure 2-1. Mc68306 Detailed Block Diagram

    IACK1 IRQ6/PB7 IRQ5/PB6 X1/CLK IRQ3/PB5 TWO- 16-BIT RxDA CHANNEL IRQ2/PB4 TIMER/ PORT B TxDA SERIAL COUNTER IACK6/PB3 RxDB IACK5/PB2 PORT A TxDB IACK3/PB1 IACK2/PB0 RTSB/OP1 FLOW RTSA/OP0 CONTROL CTSB/IP1 CTSA/IP0 Figure 2-1. MC68306 Detailed Block Diagram MC68306 USER'S MANUAL MOTOROLA...
  • Page 23: Table 2-1. Bus Signal Summary

    Table 2-3. DRAM Controller Signal Summary Input/ Three-State During Pullup Required Signal Name Mnemonic Output Bus Arbitration Column Address Strobe CAS1–CAS0 Output 4.7 K Row Address Strobe RAS1–RAS0 Output 4.7 K DRAM Write Signal Output DRAMW MOTOROLA MC68306 USER'S MANUAL 2- 3...
  • Page 24: Table 2-4. Interrupt And Parallel Port Signal Summary

    Table 2-5. Clock and Mode Control Signal Summary Input/ Three-State During Pullup Required Signal Name Mnemonic Output Bus Arbitration Crystal Oscillator or External EXTAL Input — Clock Crystal Oscillator XTAL Output — System Clock CLKOUT Output Address Mode AMODE Input — MC68306 USER'S MANUAL MOTOROLA...
  • Page 25: Bus Signals

    3. Pin has internal pullup, but external pulldown may be required for correct initialization. 2.1 BUS SIGNALS The following signals are used for the MC68306 bus. 2.1.1 Address Bus (A23–A1) This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
  • Page 26: Address Strobe (As)

    Assertion of this bi-directional, open-drain signal indicates a problem in the current bus cycle. The MC68306 can assert this signal to terminate a bus cycle when no external response is received. An external source can assert BERR to indicate a problem such as: 1.
  • Page 27: Data Bus (D15-D0)

    BGACK can be negated (pulled high), and the MC68306 will operate in a two-wire bus arbitration system. 2.1.7 Data Bus (D15–D0) This bi-directional, three-state bus is the general-purpose data path. It is 16 bits wide and can transfer and accept data of either word or byte length. During an interrupt acknowledge cycle, an external device can supply the interrupt vector number on data lines D7–D0.
  • Page 28: Read/Write (R/W)

    Operation. Processor assertion of HALT indicates a double bus fault condition. This condition is unrecoverable; the MC68306 must be externally reset to resume operation. 2.1.12 Read/Write (R/ This three-state, bi-directional signal defines the data bus transfer as a read or write cycle.
  • Page 29: Lower Byte Write (Lw )

    CS7 –CS4 are only available in chip select mode (AMODE bit =1). CS3–CS0 are always available. 2.3 DRAM CONTROLLER SIGNALS The following signals are used to control an external DRAM for the MC68306. CAS1 CAS0 2.3.1 Column Address Strobe ( –...
  • Page 30: Interrupt Request (Irq7-Irq1)

    A23–A20 is selected and when set to one, CS7–CS4 is selected. The mode selection is static: AMODE is latched at the end of any system reset. 2.6 SERIAL MODULE SIGNALS The following paragraphs describe the signals used by the serial module on the MC68306. 2-10 MC68306 USER'S MANUAL...
  • Page 31: Channel A Receiver Serial-Data Input (Rxda)

    This output can be used as a general-purpose output or the channel B active low request- to-send (RTSB) output. When used for this function, it is automatically negated and reasserted by either the receiver or transmitter. MOTOROLA MC68306 USER'S MANUAL 2- 11...
  • Page 32: Crystal Oscillator (X1, X2)

    This output is used for serial test instructions and test data for on-chip test logic defined by the IEEE 1149.1 standard. TRST 2.7.5 Test Reset ( This input is the master reset for on-chip test logic defined by the IEEE 1149.1 standard. 2-12 MC68306 USER'S MANUAL MOTOROLA...
  • Page 33: 68000 Bus Operation Description

    A0 bit to determine which byte to read and issues the appropriate data strobe. When A0 is zero, the upper data strobe is issued; when A0 is one, the lower data strobe is issued. When the data is received, the processor internally positions the byte appropriately. MOTOROLA MC68306 USER'S MANUAL 3- 1...
  • Page 34: Figure 3-1. Word Read Cycle Flowchart

    ACQUIRE THE DATA ACKNOWLEDGE (DTACK) 1) LATCH DATA 2) NEGATE UDS AND LDS 3) NEGATE AS TERMINATE THE CYCLE 1) REMOVE DATA FROM D7–D0 OR D15–D8 2) NEGATE DTACK START NEXT CYCLE Figure 3-2. Byte Read Cycle Flowchart MC68306 USER'S MANUAL MOTOROLA...
  • Page 35: Figure 3-3. Read And Write Cycle Timing Diagram

    S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 FC2–FC0 A31–A1 A0 * DTACK D15–D8 D7–D0 READ WRITE READ *Internal Signal Only Figure 3-4. Word and Byte Read Cycle Timing Diagram MOTOROLA MC68306 USER'S MANUAL 3- 3...
  • Page 36: Write Cycle

    UDS and LDS and writes both bytes. A long-word write is accomplished by two consecutive word writes. When the instruction specifies a byte operation, the processor uses the internal A0 bit to determine which byte to write and issues the appropriate data MC68306 USER'S MANUAL MOTOROLA...
  • Page 37: Figure 3-5. Word Write Cycle Flowchart

    TERMINATE OUTPUT TRANSFER 1) NEGATE UDS AND LDS 2) NEGATE AS 3) REMOVE DATA FROM D15–D0 4) SET R/W TO READ TERMINATE THE CYCLE 1) NEGATE DTACK START NEXT CYCLE Figure 3-5. Word Write Cycle Flowchart MOTOROLA MC68306 USER'S MANUAL 3- 5...
  • Page 38: Figure 3-6. Byte Write Cycle Flowchart

    S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 FC2–FC0 A31–A1 DTACK D15–D8 D7–D0 *INTERNAL SIGNAL ONLY EVEN BYTE WRITE WORD WRITE ODD BYTE WRITE Figure 3-7. Word and Byte Write Cycle Timing Diagram MC68306 USER'S MANUAL MOTOROLA...
  • Page 39: Read-Modify-Write Cycle

    The test and set (TAS) instruction uses this cycle to provide a signaling capability without deadlock between processors in a multiprocessing environment. The TAS instruction (the only instruction MOTOROLA MC68306 USER'S MANUAL 3- 7...
  • Page 40: Figure 3-8. Read-Modify-Write Cycle Flowchart

    TERMINATE OUTPUT TRANSFER 1) NEGATE UDS OR LDS 2) NEGATE AS 3) REMOVE DATA FROM D7–D0 OR D15–D8 TERMINATE THE CYCLE 4) SET R/W TO READ 1) NEGATE DTACK START NEXT CYCLE Figure 3-8. Read-Modify-Write Cycle Flowchart MC68306 USER'S MANUAL MOTOROLA...
  • Page 41: Figure 3-9. Read-Modify-Write Cycle Timing Diagram

    UDS /LDS . The device negates DTACK at this time. STATES 8–11 The bus signals are unaltered during S8–S11, during which the arithmetic logic unit makes appropriate modifications to the data. MOTOROLA MC68306 USER'S MANUAL 3- 9...
  • Page 42 During S7, no bus signals are altered. STATE 8 During S8, no bus signals are altered. STATE 9 AS and U D S /LDS are negated. The cycle terminates without the write portion. Case W2: BERR only on write. 3-10 MC68306 USER'S MANUAL MOTOROLA...
  • Page 43: Cpu Space Cycle

    A3–A1 and drives all other address lines high. The interrupt acknowledge cycle reads a vector number when the device places a vector number on the data bus. The timing diagram for an interrupt acknowledge cycle is shown in Figure 3-11. MOTOROLA MC68306 USER'S MANUAL 3- 11...
  • Page 44: Bus Arbitration

    Figure 3-12 is a flowchart showing the bus arbitration cycle of the EC000 core. Figure 3- 13 is a timing diagram of the bus arbitration cycle charted in Figure 3-12. This technique allows processing of bus requests during data transfer cycles. 3-12 MC68306 USER'S MANUAL MOTOROLA...
  • Page 45: Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart

    1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PRO- CESSOR USES RELEASE BUS MASTERSHIP 1) NEGATE BGACK REARBITRATE OR RESUME PROCESSOR OPERATION Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart MOTOROLA MC68306 USER'S MANUAL 3- 13...
  • Page 46: Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart

    2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE ACKNOWLEDGE RELEASE OF RELEASE BUS MASTERSHIP BUS MASTERSHIP 1) NEGATE BUS REQUEST (BR) 1) NEGATE BUS GRANT (BG) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart 3-14 MC68306 USER'S MANUAL MOTOROLA...
  • Page 47: Figure 3-14. Three-Wire Bus Arbitration Timing Diagram

    Figure 3-14. Three-Wire Bus Arbitration Timing Diagram S2 S4 S0 S2 S4 S6 S0 S2 S4 S6 S0 S2 S4 S6 FC2–FC0 A19–A0 DTACK D7–D0 PROCESSOR DMA DEVICE PROCESSOR DMA DEVICE Figure 3-15. Two-Wire Bus Arbitration Timing Diagram MOTOROLA MC68306 USER'S MANUAL 3- 15...
  • Page 48: Requesting The Bus

    BGACK . BGACK should not be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus by negating BGACK . 3-16 MC68306 USER'S MANUAL MOTOROLA...
  • Page 49: Bus Arbitration Control

    A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 3-18. The bus arbitration timing while the bus is inactive (e.g., the processor is performing internal operations for a multiply instruction) is shown in Figure 3-19. MOTOROLA MC68306 USER'S MANUAL 3- 17...
  • Page 50: Figure 3-17. Bus Arbitration Unit State Diagrams

    2. The address bus will be placed in T = Three-state Control to Bus Control Logic the high-impedance state if T is X = Don't Care asserted and AS is negated. Figure 3-17. Bus Arbitration Unit State Diagrams 3-18 MC68306 USER'S MANUAL MOTOROLA...
  • Page 51: Figure 3-18. Three-Wire Bus Arbitration Timing Diagram-Processor Active

    S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 BGACK FC2–FC0 A31–A1 DTACK D15–D0 ALTERNATE BUS MASTER PROCESSOR PROCESSOR Figure 3-18. Three-Wire Bus Arbitration Timing Diagram—Processor Active MOTOROLA MC68306 USER'S MANUAL 3- 19...
  • Page 52: Figure 3-19. Three-Wire Bus Arbitration Timing Diagram-Bus Inactive

    BR SAMPLED BR ASSERTED S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 BGACK FC2–FC0 A31–A1 DTACK D15–D0 ALTERNATE BUS MASTER PROCESSOR PROCESSOR INACTIVE Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive 3-20 MC68306 USER'S MANUAL MOTOROLA...
  • Page 53: Figure 3-20. Three-Wire Bus Arbitration Timing Diagram-Special Case

    PROCESSOR STARTS NEXT BUS CYCLE BR VALID INTERNAL BGACK NEGATED INTERNAL BR SAMPLED BGACK SAMPLED BR ASSERTED BGACK NEGATED BGACK FC2–FC0 A31–A1 DTACK D15–D0 ALTERNATE BUS MASTER PROCESSOR PROCESSOR Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case MOTOROLA MC68306 USER'S MANUAL 3- 21...
  • Page 54: Figure 3-21. Two-Wire Bus Arbitration Timing Diagram-Processor Active

    S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 BGACK FC2–FC0 A31–A1 DTACK D15–D0 ALTERNATE BUS MASTER PROCESSOR PROCESSOR Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active 3-22 MC68306 USER'S MANUAL MOTOROLA...
  • Page 55: Figure 3-22. Two-Wire Bus Arbitration Timing Diagram-Bus Inactive

    BR ASSERTED S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 BGACK FC2–FC0 A31–A1 DTACK D15–D0 ALTERNATE BUS MASTER PROCESSOR PROCESSOR INACTIVE Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive MOTOROLA MC68306 USER'S MANUAL 3- 23...
  • Page 56: Bus Error And Halt Operation

    (DTACK and BERR together) or S9 (BERR alone) for a read cycle, a write cycle, or the read portion of a read-modify-write cycle. For the write portion of a read-modify-write cycle, the current bus cycle is terminated in S19 (DTACK and BERR together) or S21 3-24 MC68306 USER'S MANUAL MOTOROLA...
  • Page 57: Retrying The Bus Cycle

    The assertion of the bus error signal during a bus cycle in which HALT is also asserted by an external device initiates a retry operation. Figure 3-25 is a timing diagram of the retry operation. MOTOROLA MC68306 USER'S MANUAL 3- 25...
  • Page 58: Halt Operation

    While the processor is halted, bus arbitration is performed as usual. Should a bus error occur while HALT is asserted, the processor performs the retry operation previously described. NOTE If a RESET instruction is executed while HALT is asserted, the CPU will be reset. 3-26 MC68306 USER'S MANUAL MOTOROLA...
  • Page 59: Double Bus Fault

    (before the first instruction is executed). The reset operation is described in the following paragraph. 3.5 RESET OPERATION RESET is asserted externally for the initial processor reset. Subsequently, the signal can be asserted either externally or internally (executing a RESET instruction). MOTOROLA MC68306 USER'S MANUAL 3- 27...
  • Page 60: The Relationship Of Dtack, Berr , And Halt

    Cycles) for both of them is met during the same bus state. External circuitry should be designed to incorporate this precaution. A related specification, #48, can be ignored when DTACK, BERR , and HALT are asserted and negated on the rising edge of the processor clock. 3-28 MC68306 USER'S MANUAL MOTOROLA...
  • Page 61 NA — Signal not asserted in this bus state X — Don't care S — Signal asserted in preceding bus state and remains asserted in this state NOTE: All operations are subject to relevant setup and hold times. MOTOROLA MC68306 USER'S MANUAL 3- 29...
  • Page 62: Asynchronous Operation

    BERR , or BERR and HALT, to abort or retry the cycle. Figure 3-28 shows the use of the bus handshake signals in a fully asynchronous read cycle. Figure 3-29 shows a fully asynchronous write cycle. 3-30 MC68306 USER'S MANUAL MOTOROLA...
  • Page 63: Figure 3-28 Fully Asynchronous Read Cycle

    Parameter #11 (refer to AC Electrical Specifications—Read and Write Cycles) specifies the minimum time before address strobe during which the address is valid. MOTOROLA MC68306 USER'S MANUAL 3- 31...
  • Page 64: Figure 3-30. Pseudo-Asynchronous Read Cycle

    If DTACK remains asserted past the time specified by parameter #28, the processor may recognize it as being asserted early in the next bus cycle and may terminate that cycle prematurely. Figure 3-31 shows the important timing specifications for a pseudo-asynchronous write cycle. 3-32 MC68306 USER'S MANUAL MOTOROLA...
  • Page 65: Synchronous Operation

    R/W . The minimum value for parameter #18 applies to a read cycle preceded by a write cycle; this value is the maximum hold time for a low on R/W beyond the initiation of the read cycle. MOTOROLA MC68306 USER'S MANUAL 3- 33...
  • Page 66 The hold time for data relative to the negation of A S and U D S /LDS is specified by parameter #29. For a write cycle, only AS and UDS /LDS , are negated; timing parameter #12 also applies. 3-34 MC68306 USER'S MANUAL MOTOROLA...
  • Page 67: Figure 3-32. Synchronous Read Cycle

    Figure 3-32 shows a synchronous read cycle and the important timing parameters that apply. The timing for a synchronous read cycle, including relevant timing parameters, is shown in Figure 3-33. CLOCK ADDR UDS/LDS DTACK DATA Figure 3-32. Synchronous Read Cycle MOTOROLA MC68306 USER'S MANUAL 3- 35...
  • Page 68: Figure 3-33. Synchronous Write Cycle

    #27 has been met, parameter #31 may be ignored. If DTACK is asserted with the required setup time before the falling edge of S4, no wait states are incurred, and the bus cycle runs at its maximum speed of four clock periods. 3-36 MC68306 USER'S MANUAL MOTOROLA...
  • Page 69: Ec000 Core Processor

    Note that when the processor executes a STOP instruction, it is in a special type of normal processing state, one without bus cycles. The processor stops, but it does not halt. MOTOROLA MC68306 USER'S MANUAL 4- 1...
  • Page 70: Programming Model

    ADDRESS REGISTERS A7/USP USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER USER PROGRAMMING MODEL SUPERVISOR STACK POINTER (CCR) STATUS REGISTER (CCR IS ALSO SHOWN IN THE USER PROGRAMMING MODEL) SUPERVISOR PROGRAMMING MODEL Figure 4-1. Programmer's Model MC68306 USER'S MANUAL MOTOROLA...
  • Page 71: Data Format Summary

    Operand Data Format Size Notes 1 Bit — Binary-Coded Decimal (BCD) 8 Bits Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte Byte Integer 8 Bits — Word Integer 16 Bits — Long-Word Integer 32 Bits — MOTOROLA MC68306 USER'S MANUAL 4- 3...
  • Page 72: Addressing Capabilities Summary

    An ¨ An–N, EA=(An) Register Indirect with Offset EA=(An)+d 16 Indexed Register Indirect with Offset EA=(An)+(Xn)+d 8 Immediate Data Addressing Immediate DATA=Next Word(s) Quick Immediate Inherent Data Implied Addressing Implied Register EA=SR, USP, SSP, PC, VBR, SFC, DFC MC68306 USER'S MANUAL MOTOROLA...
  • Page 73: Notation Conventions

    Data register’s remainder or quotient of divide. Data register D7–D0, used during update. Dx, Dy Source and destination data registers, respectively. Any Address or Data Register Rx, Ry Any source and destination registers, respectively. Index Register—An, Dn, or suppressed. MOTOROLA MC68306 USER'S MANUAL 4- 5...
  • Page 74 A scale factor (1, 2, 4, or 8, for no-word, word, long-word, or quad-word scaling, respectively). SIZE The index register’s size (W for word, L for long word). {offset:width} Bit field selection. Register Names Condition Code Register (lower byte of status register) Program Counter Status Register MC68306 USER'S MANUAL MOTOROLA...
  • Page 75: Ec000 Core Instruction Set Overview

    Register Codes General Case. Carry Bit in CCR Condition Codes from CCR Function Code Negative Bit in CCR Undefined, Reserved for Motorola Use. Overflow Bit in CCR Extend Bit in CCR Zero Bit in CCR — Not Affected or Applicable.
  • Page 76: Table 4-4. Ec000 Core Instruction Set Summary

    If Dn < 0 or Dn > Source CHK <ea>,Dn then TRAP 0 ˘ Destination CLR <ea> Destination – Source ˘ cc CMP <ea>,Dn CMPA Destination – Source CMPA <ea>,An CMPI Destination – Immediate Data CMPI #<data>,<ea> MC68306 USER'S MANUAL MOTOROLA...
  • Page 77 MOVE <ea>,CCR MOVE to SR If supervisor state MOVE <ea>,SR then Source ˘ SR else TRAP MOVE USP If supervisor state MOVE USP,An then USP ˘ An or An ˘ USP MOVE An,USP else TRAP MOTOROLA MC68306 USER'S MANUAL 4- 9...
  • Page 78 SP + 4 ˘ SP; restore state and deallocate stack according to (SP) else TRAP (SP) ˘ CCR; SP + 2 ˘ SP; (SP) ˘ PC; SP + 4 ˘ SP (SP) ˘ PC; SP + 4 ˘ SP 4-10 MC68306 USER'S MANUAL MOTOROLA...
  • Page 79 Destination Tested ˘ Condition Codes TST <ea> UNLK An ˘ SP; (SP) ˘ An; SP + 4 ˘ SP UNLK An NOTES: 1. d is direction, left or right. 2. List refers to register. MOTOROLA MC68306 USER'S MANUAL 4- 11...
  • Page 80: Exception Processing

    For all other exceptions, internal logic provides the vector number. This vector number is used in the last step to calculate the address of the exception vector. Throughout this section, vector numbers are given in decimal notation. 4-12 MC68306 USER'S MANUAL MOTOROLA...
  • Page 81: Figure 4-3. General Exception Processing Flowchart

    HANDLER (DOUBLE BUS FAULT) BUS ERROR OR ADDRESS ERROR OTHERWISE BEGIN INSTRUCTION EXECUTION (DOUBLE BUS FAULT) EXIT EXIT NOTE: These blocks vary for reset and interrupt exceptions. EC28 Figure 4-3. General Exception Processing Flowchart MOTOROLA MC68306 USER'S MANUAL 4- 13...
  • Page 82: Exception Vectors

    32-bit long-word vector offset. In the EC000 core this offset is used as the absolute address to obtain the exception vector itself, which is illustrated in Figure 4-6. 4-14 MC68306 USER'S MANUAL MOTOROLA...
  • Page 83: Figure 4-5. Exception Vector Format

    Of the 255, 192 are reserved for user interrupt vectors. However, the first 64 entries are not protected, so user interrupt vectors may overlap at the discretion of the systems designer. MOTOROLA MC68306 USER'S MANUAL 4- 15...
  • Page 84: Processing Of Specific Exceptions

    User Defined Vectors NOTES: Vector numbers 12, 13, 16–23, and 48–63 are reserved for future enhancements by Motorola. No user peripheral devices should be assigned these numbers. Reset vector (0) requires four words, unlike the other vectors which only require two words, and is located in the supervisor program space.
  • Page 85: Reset Exception

    If external logic requests an automatic vector, the processor internally generates a vector number corresponding to the interrupt level number. If external logic indicates a bus error, MOTOROLA MC68306 USER'S MANUAL 4- 17...
  • Page 86: Uninitialized Interrupt Exception

    Illegal instruction is the term used to refer to any of the word bit patterns that do not match the bit pattern of the first word of a legal processor instruction. If such an instruction is fetched, an illegal instruction exception occurs. Motorola reserves the right to define 4-18...
  • Page 87: Privilege Violations

    M68000 family-compatible microprocessors. The patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer use (as the take illegal instruction trap (ILLEGAL) instruction).
  • Page 88: Bus Error

    Although this information is not generally sufficient to effect full recovery from the bus 4-20 MC68306 USER'S MANUAL MOTOROLA...
  • Page 89: Address Error

    Within group 1, trace has priority over external interrupts, which in turn takes priority over illegal instruction and privilege violation. Since only one instruction can be executed at a time, no priority relationship applies within group 2. MOTOROLA MC68306 USER'S MANUAL 4- 21...
  • Page 90: Table 4-6. Exception Grouping And Priority

    This rule does not apply to the reset exception; its handler is executed first even though it has the highest priority, because the reset operation clears all other exceptions. 4-22 MC68306 USER'S MANUAL MOTOROLA...
  • Page 91: System Operation

    See Individual Descriptions 5.1 MC68306 ADDRESS SPACE The full 32-bit address capability of the MC68306 (corresponding to a 4-Gbyte address space) is decoded internally. A small portion of this address space is devoted to internal resources such as the serial module, configuration registers, and parallel ports. Table 5-1 is a memory map of the MC68306.
  • Page 92: Table 5-1. Mc68306 Memory Map

    Table 5-1. MC68306 Memory Map A(31–0) D(15–8) (EVEN ADDRESS) D(7–0) (ODD ADDRESS) FFFFFFFE/F SYSTEM TIMER VECTOR FFFFFFFC/D REFRESH RATE BUS TIMEOUT PERIOD FFFFFFFA INTERRUPT CONTROL REGISTER FFFFFFF8 INTERRUPT STATUS REGISTER FFFFFFF6 RESERVED FFFFFFF4/5 PORT A PIN ASSIGNMENT PORT B PIN ASSIGNMENT...
  • Page 93: Register Description

    5.2 REGISTER DESCRIPTION The following paragraphs describe the registers in the MC68306. The address of the register is listed above the register. The numbers in the first row are the bit positions of each bit in the register. The second row is the bit mnemonic. The reset value for each bit is listed beneath the bit mnemonic.
  • Page 94: Timer Vector Register

    The bus timeout timer restarts between the read and write portions of a TAS indivisible cycle. BT7–0—Bus Timeout Period The value set in this field supplies the bus timeout timer period. The bus timeout timer period can be calculated from the equation: Period = (16 (register value +1)) EXTAL MC68306 USER'S MANUAL MOTOROLA...
  • Page 95: Interrupt Registers

    Each interrupt can be auto-vectored, by programming the interrupt control register. Auto- vectored interrupt acknowledge cycles are zero wait states. If no active interrupt is present at the level being acknowledged, the MC68306 automatically generates a spurious interrupt vector, which is a zero wait state. Interrupt input synchronization is frozen during an interrupt acknowledge cycle, so the acknowledge can safely be used to automatically negate the interrupt.
  • Page 96: Interrupt Status Register

    The port data register is not affected by any reset, so it should be initialized before enabling any bits as outputs. MC68306 USER'S MANUAL MOTOROLA...
  • Page 97: Port Pins Register

    The port direction register bits determine the direction of data flow at the port pins. PADIR7–0—Port A Direction Register Bit 7–0 This bit determines the direction of data flow at port A pins 7 through 0. 0 = Input. 1 = Output. PBDIR7–0—Port B Direction Register Bit 7–0 MOTOROLA MC68306 USER'S MANUAL 5- 7...
  • Page 98: Port Data Register

    CS0 responds to 00000000–FFFFEFFF. The other chip selects are not affected by any reset, and must be explicitly programmed. This applies to all chip selects, whether used or not. MC68306 USER'S MANUAL MOTOROLA...
  • Page 99: Chip Select Configuration Registers (High Half)

    They can be disabled, or they can be used to provide automatic DTACK timing for externally decoded resources. If more decodes are necessary than are supplied on the MC68306, one of the existing chip selects should be used (Figure 5-1) to enable the external decoding, since some signals used to qualify the chip selects are not available externally.
  • Page 100: Chip Select Configuration Registers (Low Half)

    0000 = A31–A17 ignored in chip select address match 0001 = A31 must match CSA31; A30–A17 ignored in chip select address match 0010 = A31–A30 must match CSA31–CSA30; A29–A17 ignored in chip select address match 5-10 MC68306 USER'S MANUAL MOTOROLA...
  • Page 101: Table 5-2. Chip Select Match Bits

    1101 = Automatic DTACK, 13 wait states 0110 = Automatic DTACK, 6 wait states 1110 = Automatic DTACK, 14 wait states 0111 = Automatic DTACK, 7 wait states 1111 = No automatic DTACK, external DTACK required MOTOROLA MC68306 USER'S MANUAL 5- 11...
  • Page 102: Dram Control Registers

    This will not disturb the timer, and the reset recovery can proceed at leisure. Refresh stops only when the MC68306 is arbitrated off the bus. If the internal EC000 BG signal is asserted while a refresh cycle is in progress, the external BG signal is delayed until the refresh is complete.
  • Page 103: Table 5-3. Dram Address Multiplexer

    RAS address width of the DRAMs. If this is done, the DRAMA, CAS, and DRAMW signals should be buffered. This will almost certainly require the wait state. Also, DRAMs with more row address pins than column address pins are supported. MOTOROLA MC68306 USER'S MANUAL 5- 13...
  • Page 104: Dram Refresh Register

    0 = Write cycles are inhibited to DRAM bank space 1 = Write cycles are permitted to DRAM bank space NOTE Never perform a TAS instruction to DRAM if the DRAM is configured as write-only. 5-14 MC68306 USER'S MANUAL MOTOROLA...
  • Page 105: Dram Bank Configuration Register (Low Half)

    0010 = A31–A30 must match DRA31–DRA30; A29–A17 ignored in DRAM bank address match ..1111 = A31–A17 must match DRA31–DRA17 in DRAM bank address match Table 5-4 shows the entire range of address bits that must match for a DRAM bank to occur. MOTOROLA MC68306 USER'S MANUAL 5- 15...
  • Page 106: Table 5-4. Dram Bank Match Bits

    DRDT—DRAM Automatic DTACK Response 0 = Automatic DTACK, 0 wait states 1 = Automatic DTACK, 1 wait state NOTE The write portion of a TAS is always 0-wait, regardless of the state of DRDT. 5-16 MC68306 USER'S MANUAL MOTOROLA...
  • Page 107: Automatic Dtack Generation

    C + C1. is the total output capacitance, consisting of C2 and external parasitic capacitances (e.g., board and package capacitances). MOTOROLA MC68306 USER'S MANUAL 5- 17...
  • Page 108: Figure 5-2. Oscillator Circuit Diagram

    C EXT XTAL, X2 EXTAL, X1 10 M 12 pf 15 pf MC68306 Figure 5-2. Oscillator Circuit Diagram 5-18 MC68306 USER'S MANUAL MOTOROLA...
  • Page 109: Serial Module

    SECTION 6 SERIAL MODULE The MC68306 serial module is a dual universal asynchronous/synchronous receiver/ transmitter that interfaces directly to the CPU. The serial module, shown in Figure 6-1, consists of the following major functional areas: • Two Independent Serial Communication Channels (A and B) •...
  • Page 110: Module Overview

    • Timer/Counter Interrupt Can Be Independently Programmed • Parity, Framing, and Overrun Error Detection • False-Start Bit Detection • Line-Break Detection and Generation • Detection of Breaks Originating in the Middle of a Character • Start/End Break Interrupt/Status MC68306 USER'S MANUAL MOTOROLA...
  • Page 111: Serial Communication Channels A And B

    The interrupt level of the serial module IRQ is programmed in the system register external to the serial module. When an interrupt at this level is acknowledged, the serial module is serviced before the external IRQ7 of the same level. MOTOROLA MC68306 USER'S MANUAL...
  • Page 112: Comparison Of Serial Module To Mc68681

    ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal on the falling edge of the clock source, with the least significant bit transmitted first. MC68306 USER'S MANUAL MOTOROLA...
  • Page 113: Channel A Receiver Serial Data Input (Rxda)

    ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first. MOTOROLA MC68306 USER'S MANUAL...
  • Page 114: Channel B Receiver Serial Data Input (Rxdb)

    It can generate an interrupt on change-of-state. CTSB 6.2.10.1 . When used for this function, this signal is the channel B clear-to-send input. 6.2.10.2 IP1. When used for this function, this signal is a general-purpose input. MC68306 USER'S MANUAL MOTOROLA...
  • Page 115: Operation

    The functional block diagram of the transmitter and receiver, including command and operating registers, is shown in Figure 6-4. The paragraphs that follow contain descriptions for both these functions in reference to this diagram. For detailed register information, refer to 6.4 Register Description and Programming. MOTOROLA MC68306 USER'S MANUAL...
  • Page 116: Figure 6-4. Transmitter And Receiver Functional Diagram

    RECEIVER HOLDING REGISTER 3 RxDB RECEIVE RECEIVER SHIFT REGISTER BUFFER (RBB) (4 REGISTERS) NOTE: R/W = READ/WRITE R = READ W = WRITE ..Figure 6-4. Transmitter and Receiver Functional Diagram MC68306 USER'S MANUAL MOTOROLA...
  • Page 117: Figure 6-5. Transmitter Timing Diagram

    (TxEMP) in the DUSR is set. Transmission resumes and the TxEMP bit is cleared when the CPU loads a new character into the transmitter buffer (DUTB). If a disable command is sent to the transmitter, it continues operating until the character in the MOTOROLA MC68306 USER'S MANUAL...
  • Page 118: Transmitter

    RB and RxRDY bits in the DUSR are set. The RxDx signal must return to a high condition for at least one-half bit time before a search for the next start bit begins. 6-10 MC68306 USER'S MANUAL MOTOROLA...
  • Page 119: Receiver

    The receive buffer consists of the FIFO and a receiver shift register connected to the RxDx (refer to Figure 6-4). Data is assembled in the receiver shift register and loaded into the top empty receiver holding MOTOROLA MC68306 USER'S MANUAL 6-11...
  • Page 120 FIFO can still be read by the CPU. If the receiver is reset, the FIFO stack and all receiver status bits, corresponding output ports, and interrupt request are reset. No additional characters are received until the receiver is re-enabled. 6-12 MC68306 USER'S MANUAL MOTOROLA...
  • Page 121: Looping Modes

    Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected. MOTOROLA MC68306 USER'S MANUAL 6-13...
  • Page 122: Multidrop Mode

    Data fields in the data stream are separated by an address character. After a slave receives a block of data, the slave station's CPU disables the receiver and initiates the process again. 6-14 MC68306 USER'S MANUAL MOTOROLA...
  • Page 123: Figure 6-8. Multidrop Mode Timing Diagram

    A/D bit is a one (address tag). The character is discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU via the receiver holding register stack during read operations. MOTOROLA MC68306 USER'S MANUAL 6-15...
  • Page 124: Counter/Timer

    X1/CLK or an external input on input port pin IP2, divided by one or sixteen. The square wave generated by the timer has a period of twice the preload value times the period of the clock source, is available as a clock source for both communications channels, and 6-16 MC68306 USER'S MANUAL MOTOROLA...
  • Page 125: Bus Operation

    6.4.1 Register Description The operation of the serial module is controlled by writing control bytes into the appropriate registers. A list of serial module registers and their associated addresses is MOTOROLA MC68306 USER'S MANUAL 6-17...
  • Page 126: Auxiliary Control Register (Duacr)

    2. Address-triggered commands Figure 6-9. Serial Module Programming Model 6.4.1.1 MODE REGISTER 1 (DUMR1). DUMR1 controls some of the serial module configuration. This register can be read or written at any time. It is accessed when the 6-18 MC68306 USER'S MANUAL MOTOROLA...
  • Page 127 These bits encode the type of parity used for the channel (see Table 6-1). The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. These bits can alternatively select multidrop mode for the channel. MOTOROLA MC68306 USER'S MANUAL 6-19...
  • Page 128: Table 6-1. Pmx And Pt Control Bits

    DUMR1. Accesses to DUMR2 do not change the pointer. DUMR2A, DUMR2B TxRTS TxCTS RESET: Read/Write CM1–CM0—Channel Mode These bits select a channel mode as listed in Table 6-3. See 6.3.3 Looping Modes for more information on the individual modes. 6-20 MC68306 USER'S MANUAL MOTOROLA...
  • Page 129: Output Port Control Register (Duopcr)

    If an external 1 clock is used for the transmitter, DUMR2 bit 3 = 0 selects one stop bit, and DUMR2 bit 3 = 1 selects two stop bits for transmission. MOTOROLA MC68306 USER'S MANUAL 6-21...
  • Page 130: Table 6-4. Sbx Control Bits

    The received break circuit detects breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until the end of the next detected character time. 0 = No break has been received. 6-22 MC68306 USER'S MANUAL MOTOROLA...
  • Page 131 FFULL—FIFO Full 1 = A character has been received in channel B and is waiting in the receiver buffer FIFO. 0 = The FIFO is not full, but may contain up to two unread characters. MOTOROLA MC68306 USER'S MANUAL 6-23...
  • Page 132 (DUACR) bit 7. Set 1 is selected if DUACR bit 7 = 0, and set 2 is selected if DUACR bit 7 = 1. The receiver clock is always 16 times the baud rate shown in this list, except when the clock select bits = 1111. 6-24 MC68306 USER'S MANUAL MOTOROLA...
  • Page 133: Table 6-5. Rcsx Control Bits

    DUACR bit 7 = 0, and set 2 is selected if DUACR bit 7 = 1. The transmitter clock is always 16 times the baud rate shown in this list, except when the clock select bits = 1111. MOTOROLA MC68306 USER'S MANUAL 6-25...
  • Page 134: Table 6-6. Tcsx Control Bits

    DUCRA, DUCRB – MISC2 MISC1 MISC0 RESET: Write Only MISC3–MISC0—Miscellaneous Commands These bits select a single command as listed in Table 6-7. 6-26 MC68306 USER'S MANUAL MOTOROLA...
  • Page 135: Table 6-7. Miscx Control Bits

    Stop Break—The stop break command causes the channel's TxDx to go high (mark) within two bit times. Characters stored in the transmitter buffer, if any, are transmitted. TC1–TC0—Transmitter Commands These bits select a single command as listed in Table 6-8. MOTOROLA MC68306 USER'S MANUAL 6-27...
  • Page 136: Table 6-8. Tcx Control Bits

    Receiver Disable—The receiver disable command disables the receiver immediately. Any character being received is lost. The command has no effect on the receiver status bits or any other control register. If the serial module is programmed to operate in the 6-28 MC68306 USER'S MANUAL MOTOROLA...
  • Page 137 TB7–TB0—These bits contain the character in the transmitter buffer. 6.4.1.8 INPUT PORT CHANGE REGISTER (DUIPCR). The DUIPCR shows the current state and the change-of-state for the IP0, IP1, and IP2 pins. DUIPCR COS2 COS1 COS0 RESET: Read Only MOTOROLA MC68306 USER'S MANUAL 6-29...
  • Page 138 0 = Set 1 of the available baud rates is selected. Refer to 6.4.1.4 Clock-Select Register (DUCSR) for more information on the baud rates. CTMS2–0— Counter/Timer Mode and Source Select Table 6-10 lists the counter/timer mode and source select bit fields. 6-30 MC68306 USER'S MANUAL MOTOROLA...
  • Page 139: Table 6-10. Counter/Timer Mode And Source Select Bits

    1 = A change-of-state has occurred at one of the IPx inputs and has been selected to cause an interrupt by programming bit 2, 1 and/or bit 0 of the DUACR. 0 = No selected COSx in the DUIPCR. MOTOROLA MC68306 USER'S MANUAL 6-31...
  • Page 140 DUIMR is zero, the state of the bit in the DUISR has no effect on the IRQ output. The DUIMR does not mask the reading of the DUISR. DUIMR FFULLB TxRDYB CTR/TM FFULLA TxRDYA _RDY RESET: Write Only COS—Change-of-State 1 = Enable interrupt 0 = Disable interrupt 6-32 MC68306 USER'S MANUAL MOTOROLA...
  • Page 141: Count Register Current Msb Of Counter (Ducur)

    The minimum value that can be loaded on the concatenation of DUCTUR with DUCTLR is 0002 (hex). This register is write only and cannot be read by the CPU. MOTOROLA MC68306 USER'S MANUAL 6-33...
  • Page 142 These bits have the same function and value of the DUIPCR bits 1 and 0. IP5, IP4, and IP3 are not pinned out on the MC68306, and are internally set to logic one. 6.4.1.18 OUTPUT PORT CONTROL REGISTER (DUOPCR). The DUOPCR configures six bits of the 8-bit parallel DUOP for general-purpose use or for auxiliary functions serving the communication channels.
  • Page 143 RESET: Write Only NOTE OP bits 7, 6, 5, 4, and 2 are not pinned out on the MC68306; thus changing bits 7, 6, 5, 4, 1, and 0 of this register has no effect. OPCR3–OPCR2—Output Port 3 Function Select...
  • Page 144: Output Port Data Register (Duop)

    Write Only NOTE The output port bits are inverted at the pins. OP bits 7, 6, 5, 4, and 2 are not pinned out on the MC68306; thus, changing these bits has no effect. OP3, OP1, OP0 —Output Port Parallel Outputs 1 = A write cycle to the OP bit set command address sets all OP bits corresponding to one bits on the data bus.
  • Page 145: Programming

    A change- in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. MOTOROLA MC68306 USER'S MANUAL 6-37...
  • Page 146: Figure 6-10. Serial Module Programming Flowchart

    ENABLB SAVE CHANNEL A STATUS CHK2 ERRORS IN CHANNEL B POINT TO CHANNEL B CALL CHCHK ENABLE CHANNEL B'S TRANSMITTER SINITR SAVE CHANNEL B STATUS RETURN Figure 6-10. Serial Module Programming Flowchart (1 of 5) 6-38 MC68306 USER'S MANUAL MOTOROLA...
  • Page 147 TxCHK WAITED SET TRANSMITTER- TRANSMITTER TOO LONG NEVER-READY FLAG READY SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK RECEIVER WAITED SET RECEIVER- RECEIVED TOO LONG NEVER-READY FLAG CHARACTER Figure 6-10. Serial Module Programming Flowchart (2 of 5) MOTOROLA MC68306 USER'S MANUAL 6-39...
  • Page 148 SET FRAMING ERROR FLAG PRCHK RETURN HAVE PARITY ERROR SET PARITY ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER SAME AS CHARACTER TRANSMITTED SET INCORRECT CHARACTER FLAG Figure 6-10. Serial Module Programming Flowchart (3 of 5) 6-40 MC68306 USER'S MANUAL MOTOROLA...
  • Page 149 END-OF-BREAK IRQx ARRIVED CLEAR CHANGE-IN- BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR Figure 6-10. Serial Module Programming Flowchart (4 of 5) MOTOROLA MC68306 USER'S MANUAL 6-41...
  • Page 150 OUTCH CHANNEL TRANSMITTER READY SEND CHARACTER TO CHANNEL TRANSMITTER RETURN Figure 6-10. Serial Module Programming Flowchart (5 of 5) 6-42 MC68306 USER'S MANUAL MOTOROLA...
  • Page 151: Serial Module Initialization Sequence

    6.5 SERIAL MODULE INITIALIZATION SEQUENCE If the serial capability of the MC68306 is being used, the following steps are required to properly initialize the serial module. NOTE The serial module registers can be accessed by word or byte operations, but only the data byte D7–D0 is valid.
  • Page 152 • If desired, program operation of clear-to-send (TxCTS bit). • Select stop-bit length (SBx bits). Command Register (DUCR) • Enable the receiver and transmitter. 6-44 MC68306 USER'S MANUAL MOTOROLA...
  • Page 153: Ieee 1149.1 Test Access Port

    16-state controller, an instruction register, and four test data registers. A boundary scan register links all device signal pins into a single shift register. The test logic, implemented using static logic design, is independent of the device system logic. The MC68306 implementation provides the following capabilities: a.
  • Page 154: Figure 7-1. Test Access Port Block Diagram

    An overview of the MC68306 implementation of IEEE 1149.1 is shown in Figure 7-1. The MC68306 implementation includes a 16-state controller, a 3-bit instruction register, and four test registers (a 1-bit bypass register, a 124-bit boundary scan register, a 3-bit module mode register, and a 32-bit ID register).
  • Page 155: Tap Controller

    UPDATE-DR Figure 7-2. TAP Controller State Machine 7.3 BOUNDARY SCAN REGISTER The MC68306 IEEE 1149.1 implementation has a 124-bit boundary scan register. This register contains bits for all device signal and clock pins and associated control signals. MOTOROLA MC68306 USER'S MANUAL...
  • Page 156: Table 7-1. Boundary Scan Control Bits

    (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is bit 123. The second column references one of the five MC68306 cell types depicted in Figures 7-3–7-7, which describe the cell structure for each type.
  • Page 157 IO.Cell PPOE13 IO.Cell En.Cell PPOE14 En.Cell IO.Cell PPOE14 IO.Cell En.Cell PPOE15 IO.Cell IO.Cell PPOE15 IO.Cell En.Cell PPOE0 IO.Cell IO.Cell PB0/IACK2 PPOE0 IO.Cell En.Cell PPOE1 IO.Cell IO.Cell PB1/IACK3 PPOE1 IO.Cell En.Cell PPOE2 IO.Cell IO.Cell PB2/IACK5 PPOE2 En.Cell MOTOROLA MC68306 USER'S MANUAL...
  • Page 158 IO.Cell A13/DRAMA12 CPMOE En.Cell DRAMOE IO.Cell A14/DRAMA13 CPMOE O.Cell RAS1 DRAMOE IO.Cell A15/DRAMA14 CPMOE O.Cell RAS0 DRAMOE En.Cell O.Cell CAS1 DRAMOE O.Cell O.Cell CAS0 DRAMOE O.Cell O.Cell CSOE O.Cell O.Cell CSOE O.Cell O.Cell CSOE I.Cell AMODE MC68306 USER'S MANUAL MOTOROLA...
  • Page 159: Figure 7-3. Output Cell (O.cell)

    SYSTEM TO OUTPUT LOGIC BUFFER FROM CLOCK DR UPDATE DR LAST CELL Figure 7-3. Output Cell (O.Cell) TO DEVICE INPUT LOGIC TO NEXT CELL CLOCK DR FROM LAST SHIFT DR CELL Figure 7-4. Input Cell (I.Cell) MOTOROLA MC68306 USER'S MANUAL...
  • Page 160: Figure 7-5. Output Control Cell (En.cell)

    1 – EXTEST TO NEXT SHIFT DR 0 – OTHERWISE CELL OUTPUT FROM TO OUTPUT SYSTEM DRIVER LOGIC FROM PIN FROM LAST CLOCK DR UPDATE DR INPUT TO CELL SYSTEM LOGIC Figure 7-6. Bidirectional Cell (IO.Cell) MC68306 USER'S MANUAL MOTOROLA...
  • Page 161: Instruction Register

    Figure 7-8. General Arrangement for Bidirectional Pins 7.4 INSTRUCTION REGISTER The MC68306 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), the optional public ID instruction, plus one additional public instruction (CLAMP) defined by IEEE 1149.1. The...
  • Page 162: Table 7-3. Instructions

    7.4.1 EXTEST (000) The external test (EXTEST) instruction selects the 124-bit boundary scan register. EXTEST asserts internal reset for the MC68306 system logic to force a predictable benign internal state while performing external boundary scan operations. By using the TAP, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirectional pins, and d) controlling the output drive of three-state output pins.
  • Page 163: Clamp (011)

    This creates a shift-register path from TDI to the bypass register and, finally, to TDO, circumventing the 124-bit boundary scan register. This instruction is used to enhance test efficiency when a component other than the MC68306 becomes the device under test. SHIFT DR...
  • Page 164: Non-Ieee 1149.1 Operation

    Also, the MC68306 contains dynamic logic, so EXTAL must be driven by a free-running clock at all times. 7.6 NON-IEEE 1149.1 OPERATION In non-IEEE 1149.1 operation, the IEEE 1149.1 test logic must be kept transparent to the system logic by forcing the TAP controller into the test-logic-reset state. This requires either: 1.
  • Page 165: Maximum Ratings

    ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MC68306. Refer to Section 9 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature ratings.
  • Page 166: Power Considerations

    The measurement of the AC specifications is defined by the waveforms shown in Figure 8-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in that figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in Figure 8-1.
  • Page 167: Figure 8-1. Drive Levels And Test Points For Ac Specifications

    D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum). Figure 8-1. Drive Levels and Test Points for AC Specifications MOTOROLA MC68306 USER'S MANUAL 8- 3...
  • Page 168: Dc Electrical Specifications

    EXTAL Pulse Width Low 62.5 EXTAL Pulse Width High 62.5 EXTAL Rise and Fall Times t Cr — t Cf — External Clock to CLKOUT Skew (Typical) CLKOUT Pulse Width Low –5 CLKOUT Pulse Width High –5 MC68306 USER'S MANUAL MOTOROLA...
  • Page 169: Ac Electrical Specifications-Read And Write

    AS, LDS, UDS Width Negated — CLKOUT High to Control Bus High Impedance — AS, LDS, UDS Negated to R/W Invalid — CLKOUT High to R/W High (Read) CLKOUT High to R/W Low (Write) MOTOROLA MC68306 USER'S MANUAL 8- 5...
  • Page 170 (#47). For power-up, the MC68306 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the controller.
  • Page 171: Figure 8-3. Read Cycle Timing Diagram

    2. BR need fall at this time only to ensure being recognized at the end of the bus cycle. Figure 8-3. Read Cycle Timing Diagram MOTOROLA MC68306 USER'S MANUAL 8- 7...
  • Page 172: Figure 8-4. Write Cycle Timing Diagram

    2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specification #20A). 3. BR need fall at this time only to ensure being recognized at the end of the bus cycle. Figure 8-4. Write Cycle Timing Diagram MC68306 USER'S MANUAL MOTOROLA...
  • Page 173: Ac Electrical Specifications-Chip Selects

    CLKOUT FC2–FC0, A23–A0 (NOTE 1) LDS / UDS IACKx DATA UW, LW NOTE: THE WRITE CYCLE ILLUSTRATED IS PART OF A TEST AND SET INSTRUCTION. Figure 8-5. Chip Select and Interrupt Acknowledge Timing Diagram MOTOROLA MC68306 USER'S MANUAL 8- 9...
  • Page 174: Ac Electrical Specifications-Bus Arbitration

    BG Asserted to Control, Address, Data Bus High Impedance (AS Negated) — BG Width Negated — Clks Asynchronous Input Setup Time — BGACK Negated to Bus Driven — Clks BR Negated to Bus Driven — Clks FC2–FC0 A19–A0 D7–D0 Figure 8-6. Bus Arbitration Timing Diagram 8-10 MC68306 USER'S MANUAL MOTOROLA...
  • Page 175: Figure 8-7. Bus Arbitration Timing Diagram

    Figure 8-7. Bus Arbitration Timing Diagram MOTOROLA MC68306 USER'S MANUAL 8- 11...
  • Page 176: Bus Operation-Dram Accesses Ac Timing Specifications

    DRAMW High Hold After RAS≈ Asserted (Refresh Cycle) – – NOTES: 1. On write portion of TAS, CAS assertion is gated by UDS/LDS (not CLKOUT as in all other operation). 2. Page mode is used on Read-Modify-Write (TAS instruction) cycles only. 8-12 MC68306 USER'S MANUAL MOTOROLA...
  • Page 177: Figure 8-8. Dram Timing - 0-Wait Read, No Refresh

    CLKOUT FC0–FC2 A15/DRAMA 14– A1/DRAMA 0 UDS, LDS UW, LW DTACK D15–D0 DRAMW Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh MOTOROLA MC68306 USER'S MANUAL 8- 13...
  • Page 178: Figure 8-9. Dram Timing - 1-Wait Write, No Refresh

    A15/DRAMA 14– A1/DRAMA 0 UDS, LDS UW, LW DTACK D15–D0 DRAMW Figure 8-9. DRAM Timing – 1-Wait Write, No Refresh 1-WAIT STATE 0-WAIT STATE CLKOUT DRAMW Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh 8-14 MC68306 USER'S MANUAL MOTOROLA...
  • Page 179: Serial Module Electrical Characteristics

    2. To use the standard baud rates selected by the clock-select register given in Tables 6-5 and 6-6, the X1/CLK frequency should be set to 3.6864 MHz or a 3.6864 MHz crystal should be connected across pins X1/CLK and X2. 3. IP5–2 for RxC, TxC are not supported in the MC68306. MOTOROLA...
  • Page 180: Serial Module Ac Electrical Characteristics-Clock Timing

    PD — NOTE: Test conditions for port outputs: C L = 50 pF, R L = 27 k to V CC . IP0-IP2 OP0, OP1, OP3 OLD DATA NEW DATA Figure 8-13. Port Timing 8-16 MC68306 USER'S MANUAL MOTOROLA...
  • Page 181: Ac Electrical Characteristics-Interrupt Reset

    * CTS is an asynchronous input. This specification is only provided to guarantee CTS recognition on a particular Tx clock edge. 1 BIT TIME Tx CLOCK SOURCE (X1 OR IP2) OP0, OP1 WHEN USED AS TxRTS t CH IP0, IP1 WHEN USED AS CTS t CS Figure 8-15. Transmit Timing MOTOROLA MC68306 USER'S MANUAL 8- 17...
  • Page 182: Ac Electrical Characteristics-Receiver Timing

    RxD Data Hold Time from RxC High t RxH — RTS Output Valid from Rx Clock t RRD — Rx CLOCK SOURCE (X1 OR IP2) t RRD OP0, OP1 * * When used as RxRTS Figure 8-16. Receive Timing 8-18 MC68306 USER'S MANUAL MOTOROLA...
  • Page 183: Ieee 1149.1 Electrical Characteristics

    TMS, TDI Data Setup Time — TMS, TDI Data Hold Time — TCK Low to TDO Data Valid TCK Low to TDO High Impedance TRST Width Low — Figure 8-17. Test Clock Input Timing Diagram MOTOROLA MC68306 USER'S MANUAL 8- 19...
  • Page 184: Figure 8-18. Boundary Scan Timing Diagram

    DATA OUTPUT DATA VALID OUTPUTS DATA OUTPUTS DATA OUTPUT DATA VALID OUTPUTS Figure 8-18. Boundary Scan Timing Diagram TCLK INPUT DATA VALID OUTPUT DATA VALID OUTPUT DATA VALID Figure 8-19. Test Access Port Timing Diagram 8-20 MC68306 USER'S MANUAL MOTOROLA...
  • Page 185: Ordering Information And Mechanical Data

    SECTION 9 ORDERING INFORMATION AND MECHANICAL DATA This section contains the ordering information, pin assignments, and package dimensions for the MC68306. 9.1 STANDARD ORDERING INFORMATION Package Type Frequency (MHz) Temperature Order Number 132-Lead Plastic Quad Flat Pack (FC Suffix) 8–16.7...
  • Page 186: Pin Assignments

    132-Lead Plastic Quad Flat Pack (PQFP) A21/CS5 A20/CS4 OP1/RTSB OP0/RTSA IP1/CTSB IP0/CTSA TXDB CAS0 RXDB CAS1 TXDA RAS0 RXDA RAS1 DRAMW TOP VIEW BGACK PB0/IACK2 EXTAL PB1/IACK3 XTAL PB2/IACK5 CLKOUT PB3/IACK6 HALT PB4/IRQ2 RESET PB5/IRQ3 PB6/IRQ5 MC68306 USER'S MANUAL MOTOROLA...
  • Page 187 144-Lead Thin Quad Flat Pack (TQFP) OP1/RTSB A21/CS5 A20/CS4 OP0/RTSA IP1/CTSB IP0/CTSA TXDB RXDB TXDA CAS0 RXDA CAS1 RAS0 RAS1 DRAMW MC68306 144-PIN TQFP (TOP VIEW) BGACK PB0/IACK2 PB1/IACK3 EXTAL PB2/IACK5 XTAL CLKOUT PB3/IACK6 PB4/IRQ2 HALT PB5/IRQ3 RESET PB6/IRQ5 MOTOROLA MC68306 USER'S MANUAL 9- 3...
  • Page 188: Package Dimensions

    6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM -T-. 7. DIMENSIONS A, B, N AND R TO BE DETERMINED AT DATUM PLANE -W- . 27.88 28.01 1.097 1.103 27.88 28.01 1.097 1.103 27.31 27.55 1.075 1.085 27.31 27.55 1.075 1.085 MC68306 USER'S MANUAL MOTOROLA...
  • Page 189 144-Lead Thin Quad Flat Pack (PV Suffix) MOTOROLA MC68306 USER'S MANUAL 9- 5...
  • Page 190 Normalized Numbers, 4-3 Request Signals, 6-3 Zeros, 4-3 Request, 4-17 Double Bus Fault, 3-29 Status Register, 5-6 DRAM Priority Mask, 4-12 Configuration Register, 5-14 Refresh Register, 5-13 DTACK, 3-4, 3-7, 3-10, 3-33, 3-37 DUACR, 6-30 MOTOROLA MC68306 USER’S MANUAL Index-1...
  • Page 191 Serial Module Counter/Timer Interrupt, 6-4 Single Step, 3-28 Stack Frame, 4-14 Status Register, 4-12 System Register, 5-3 — T — TAP, 7-1 TAS, 3-7 Three-Wire Bus Arbitration, 3-12 Timer Mode, 6-16 Timer Vector Register, 5-4 Index-2 MC68306 USER’S MANUAL MOTOROLA...