Motorola PowerQUICC II MPC8280 Series Reference Manual page 1296

TC Layer Programming Mode
0
Field ALPHA
Reset
R/W
Figure 35-6. Cell Delineation State Machine Registers (CDSMRx)
Table 35-3 describes CDSMR fields.
Bits Name
0-4 ALPHA ALPHA consecutive received cells with incorrect HEC are counted by the cell delineation state
machine to pass from state SYNCH to state HUNT.
5-9 DELTA DELTA consecutive received cells with correct HEC are counted by the cell delineation state
machine to pass from state PRESYNCH to state SYNCH.
10–15 — Reserved
35.4.1.3 TC Layer Event Registers 1–8 (TCERx)
The TC layer event registers (TCERx), as shown in Figure 35-7, records error events for
each TC block. TCER event bits are cleared by writing ones to them.
0 1 2
Field OR UR CDT
Reset
R/W
Figure 35-7. TC Layer Event Registers (TCERx)
The TCER bits are described in Table 35-4.
Bits Name
0 OR Overrun. Rx FIFO OverFlow.
Set when Rx FIFO is full and another complete cell is received. The cell is discarded.
1 UR Underrun. No ATM cell to transmit.
Set when the Tx FIFO is empty and the transmission of a cell is completed. An idle cell is
sent.
This interrupt is enabled only if TCMODE[URE] is set.
The idle cell header is: 0x00000001 (I.432), whose HEC is: 0x52
The idle cell payload is:0x6A (I.432).
2 CDT Cell delineation toggled.
Set when the cell delineation bit (CD) in TCGSR has changed.
35-10
Freescale Semiconductor, Inc.
4 5
0000_0000_0000_0000
Table 35-3. CDSMRx Field Descriptions
3 4 5
MS PARE
0000_0000_0000_0000
Table 35-4. TCERx Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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9 10
DELTA
R/W
Description
9 10
— ROF TOF EOF COF
R/W
Description
15
—
11 12 13 14 15
IOF FOF
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