Motorola PowerQUICC II MPC8280 Series Reference Manual page 1083

Slot N+1 is used as a control slot, as shown in Figure 31-40.
0 1 2
Field TCTE
Table 31-31 describes control slot fields.
Bits Name
0 TCTE Used for external channels only.
0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+
channels)
1 Channels in this scheduling table use external TCTE. (External VBR, ABR, UBR+ channels)
1–15 — Reserved, should be cleared.
31.10.5 ATM Controller Buffer Descriptors (BDs)
Each ATM channel has separate receive and transmit BD tables. The number of BDs per
channel and the size of the buffers is user-defined. The last BD in each table holds a wrap
indication. Each BD in the TxBD table points to a buffer to send. At the receive side, the
user can choose one of two modes:
• Static buffer allocation. In this mode, the user allocates dedicated buffers to each
ATM channel (that is, the user associates each BD with one buffer). Static buffer
allocation is useful when the connection rate is known and constant and when data
must be reassembled in a particular memory space.
• Global buffer allocation. Available for AAL5 only. In this mode, buffer allocation is
dynamic. The user allocates receive buffers and places them in global buffer pools.
When the CP needs a receive buffer, it first fetches a buffer pointer from one of the
global buffer pools and writes the pointer to the current RxBD. Global buffer
allocation is optimized for allocating memory among many ATM channels with
variable data rates, such as ABR channels.
31.10.5.1 Transmit Buffer Operation
The user prepares a table of BDs pointing to the buffers to be sent. The address of the first
BD is put in the channel's TCT[TBD_BASE]. The transmit process starts when the core
issues an
ATM TRANSMIT
associated buffer. When the current buffer is finished, the CP increments TBD_Offset,
which holds the offset from TBD_BASE to the current BD. It then reads the next BD in the
table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the current BD is not
ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which case
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
3 4 5 6
Figure 31-40. Control Slot
Table 31-31. Control Slot Field Description
command. The CP reads the first TxBD in the table and sends its
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7 8 9 10
000_0000_0000_0000
Description
ATM Memory Structure
11 12 13 14 15
31-69