Motorola PowerQUICC II MPC8280 Series Reference Manual page 1008

FCC Timing Control
5. Adjust TxBD handling as described in Section 28.10.1.3.
6. Enable FCC transmission by setting GFMR[ENT].
30.10.1.2 Recovery Sequence
1. Determine which BD is to be transmitted next and, if necessary, modify BDs.
2. Modify TBPTR field in Parameter RAM to point to next BD (if necessary).
3. Issue a "RESTART TX" command using the CPCR.
30.10.1.3 Adjusting Transmitter BD Handling
When a TXE event occurs, the TBPTR may already point beyond BDs still marked as ready
due to internal pipelining. If the TBPTR is not adjusted, these BDs would be skipped while
still being marked as ready. Software must determine if these BDs should be retransmitted
or if they should be skipped, depending on the protocol and application needs. This requires
the following steps:
1. From the current TBPTR value, search backwards over all (if any) BDs still marked
as ready to find the first BD that has not been closed by the CPM. The search process
should stop if the BD to be checked next is not ready or if it is the most recent BD
marked as ready by the CPU transmit software. This is to avoid an endless loop in
case the CPU software fills the BD ring completely.
2. A) For skipping BDs, manually close all BDs from the BD just found up to and
including the BD just before TBPTR. Leave the TBPTR value untouched.
B) For retransmitting BDs, change the TBPTR value to point to the BD just found.
30.11 FCC Timing Control
When GFMR[DIAG] is programmed to normal operation, CD and CTS are automatically
controlled by the FCC. GFMR[TCI] is assumed to be cleared, which implies normal
transmit clock operation.
RTS is asserted when FCC has data to transmit in the transmit FIFO and a falling transmit
clock occurs. At this point, the FCC begins sending the data, once the appropriate
conditions occur on CTS. In all cases, the first bit of data is the start of the opening flag, or
sync pattern.
Figure 30-9 shows that the delay between RTS and data is 0 bit times, regardless of the
setting of GFMR[CTSS]. This operation assumes that CTS is either already asserted to the
FCC or is reprogrammed to be a parallel I/O line, in which case the CTS signal to the FCC
is always asserted. RTS is negated one clock after the last bit in the frame.
30-18
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MPC8280 PowerQUICC II Family Reference Manual
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