Motorola PowerQUICC II MPC8280 Series Reference Manual page 1298

TC Layer Programming Mode
0 1 2
Field TC1 TC2 TC3
Reset
R/W
Figure 35-8. TC Layer General Event Register (TCGER)
Table 35-5 describes TCGER fields.
Bits Name
0 TC1 One bit or more is set in TC1 event register.
1 TC2 One bit or more is set in TC2 event register.
2 TC3 One bit or more is set in TC3 event register.
3 TC4 One bit or more is set in TC4 event register.
4 TC5 One bit or more is set in TC5 event register.
5 TC6 One bit or more is set in TC6 event register.
6 TC7 One bit or more is set in TC7 event register.
7 TC8 One bit or more is set in TC8 event register.
35.4.2.2 TC Layer General Status Register (TCGSR)
Figure 35-9 shows the TC layer general status register (TCGSR), which records the cell
delineation and transmit FIFO status for all TC blocks.
0 1 2
Field CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8
Reset
R/W
Figure 35-9. TC Layer General Status Register (TCGSR)
Table 35-6 describes TCGSR fields.
f
Bits Name
0–7 CDx Cell Delineation. The cell delineation state machine status of TCx.
0 Cell delineation state machine is in Hunt or Pre-Synch modes.
1 Cell delineation machine is in Synch mode.
8–15 — Reserved
35-12
Freescale Semiconductor, Inc.
3 4 5 6
TC4 TC5 TC6 TC7
0000_0000_0000_0000
Table 35-5. TCGER Field Descriptions
3 4 5 6
0000_0000_0000_0000
Table 35-6. TCGSR Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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7 8
TC8
R/W
Description
7 8
R
Description
15
—
15
—
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