Motorola PowerQUICC II MPC8280 Series Reference Manual page 870

USB Host Description
Token
IN Packet-Level Interface
Transmission begins when the USB host
controller fetches a TxBD containing an IN token
and loads the token to FIFO. After the IN token
is transmitted the USB host controller waits for
reception of data within expected time interval.
On reception of a correct DATA PID an RxBD is
fetched. The received data and DATA PID are
stored in receive FIFO. If RxBD[E] is set PID
and data will be moved to the buffer. While
receiving the data the USB host controller
calculates CRC16, performs bit un-stuffing. On
end of reception calculated CRC is compared to
received and octet alignment is checked,
RxBD[E] is cleared, RxBD[PID] is set according
to received DATA PID and error indications are
set if required:RxBD[CR] for failed CRC check,
RxBD[NO] for non-octet sized data and
RxBD[AB] if bit stuffing error occurred.
If no correct DATA PID or no data at all received
during the expected time interval a TO indication
in the token TxBD is set.
Token
IN
SETUP The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID. A SETUP
token is recognized only by a control endpoint and cannot be answered with NAK or STALL, therefore,
the host expects either an ACK or no handshake at all.
Start of SOF is generated every 1 ms. The timing must be exact and is controlled by an internal timer. From the
Frame host state machine point of view it is a packet to transmit, placed in its FIFO, transmitted as is.
(SOF)
Preamble The PRE token signals the hub that a low-speed transaction is about to occur. The PRE token is read only
(PRE) by the hub. The USB host controller generates a full-speed PRE token before sending a packet to a
low-speed peripheral.
27-12
Freescale Semiconductor, Inc.
Table 27-3. USB Tokens (continued)
Data Transmitted by
Function
Received correctly
Received corrupted
None
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Description
Transaction-Level Interface
Transmission begins when the USB host controller
fetches a TrBD with the TOK field indicating an IN
transaction. After the IN token is generated and
transmitted, the USB host controller waits for reception
of data within the expected time interval. The received
data packet is stored in buffer reference by the TrBD.
While receiving the data the USB host controller
calculates CRC16 and performs bit un-stuffing. At end
of the packet, the calculated CRC is compared to the
received value and octet alignment is checked,
TrBD[R] is cleared, TrBD[PID] is set according to the
received DATA PID and error indications are set if
required:TrBD[CR] for failed CRC check, TrBD[NO] for
non-octet sized data and TrBD[AB] if bit stuffing error
occurred. If any of the above errors are reported,
TrBD[RXER] is also set, and a TXE1 interrupt is
generated.
If no correct DATA PID or no data at all received during
the expected time interval, a TrBD[TO] is set and a
TXE1 interrupt is generated.
If no errors occurred and TrBD[I] is set, a TXB interrupt
is generated to indicate successful completion of the
transaction.
USB In Transaction
Handshake Generated
by Host
ACK
None
None
Indication on BD
RxBD[E]/TrBD[R] is
cleared
RxBD[CR]/TrBD[CR} or
RxBD[AB]/TrBD[AB] or
RxBD[NO]/TrBD[NO]
TxBD[TO]/TrBD[TO]
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