Motorola PowerQUICC II MPC8280 Series Reference Manual page 669

output can also be connected internally to the input of another timer, resulting in a 32-bit
timer.
In addition, each timer has a 16-bit TCR used to latch the value of the counter when a
defined transition of TIN1, TIN2, TIN3, or TIN4 is sensed by the corresponding input
capture edge detector. The type of transition triggering the capture is selected by the
corresponding TMR[CE] bits. Upon a capture or reference event, the corresponding TER
bit is set and a maskable interrupt request is issued to the interrupt controller. The timers
may be gated/restarted by an external gate signal. There are two gate signals—TGATE1
controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. Normal gate mode enables
the count on a falling edge of TGATEx and disables the count on the rising edge of
TGATEx. This mode allows the timer to count conditionally, based on the state of TGATEx.
The restart gate mode performs the same function as normal mode, except it also resets the
counter on the falling edge of TGATEx. This mode has applications in pulse interval
measurement and bus monitoring as follows:
• Pulse measurement—The restart gate mode can measure a low TGATEx. The rising
edge of TGATEx completes the measurement and if TGATEx is connected
externally to TINx, it causes the timer to capture the count value and generate a
rising-edge interrupt.
• Bus monitoring—The restart gate mode can detect a signal that is abnormally stuck
low. The bus signal should be connected to TGATEx. The timer count is reset on the
falling edge of the bus signal and if the bus signal does not go high again within the
number of user-defined clocks, an interrupt can be generated.
The gate function is enabled in the TMR; the gate operating mode is selected in the TGCR.
TGATEx is internally synchronized to the system clock. If
TGATEx meets the asynchronous input setup time, the counter
begins counting after one system clock when working with the
internal clock.
18.2.1 Cascaded Mode
In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter. Timer
1 may be internally cascaded to timer 2, and timer 3 can be internally cascaded to timer 4.
Because the decision to cascade timers is made independently, the user can select two
16-bit timers or one 32-bit timer. TGCR is used to put the timers into cascaded mode, as
shown in Figure 18-2.
MOTOROLA
Freescale Semiconductor, Inc.
NOTE
Chapter 18. Timers
For More Information On This Product,
Go to: www.freescale.com
General-Purpose Timer Units
18-3