Motorola PowerQUICC II MPC8280 Series Reference Manual page 1260

Freescale Semiconductor, Inc.
IMA Programming Model
34.4.8 IDCR Timer Programming
Programming of the IDCR timer data structures is optional. It is only required if any of the
IMA groups use IDCR-regulated cell processing.
Only one IDCR master clock per FCC is supported; the IDCR timers for the individual
groups are derived from the IDCR master clock. Each IDCR timer has an associated IDCR
table entry, indexed by the IMA group number.
34.4.8.1 IDCR Master Clock
The signal normally used for DMA request for a selected IDMA channel is instead used to
provide the clock signal for the IDCR master clock. This signal must be provided on the
external DREQx signal, either by using an external clock source or by externally
connecting one of the baud rate generator (BRG) outputs to the signal.
The IDCR master clock is enabled by configuring the DREQx pin and supplying the
external clock signal. The IDCR master clock is disabled by either (1) turning the clock
signal off, or (2) changing the configuration of DREQx to be an alternate function or
general-purpose I/O. The IDCR_Init command must be issued before enabling the IDCR
master clock.
A higher IDCR master clock frequency provides greater resolution in determining and
reconstructing the IDCR. However, an IDCR master clock frequency that is too high will
consume too much CPM processing power and will hinder the function of the MPC8280.
Therefore, the period of the IDCR master clock should be no less than (number of IMA
receive groups) x (500 CPM clocks).
The DONEx and DACKx signals of the IDMA channel are not used. Their I/O ports must
be programmed to an alternate function or to general-purpose I/O.
RCCR[DRxM] should be programmed to edge-sensitive for the DREQx signal functioning
as the IDCR master clock.
34.4.8.2 IDCR FCC Parameter Shadow
The FCC parameters (including IMAROOT) for the FCC associated with the IDCR master
clock must be copied onto the parameter RAM page for that IDCR master clock. For
example, if DREQ1 serves as the IDCR master clock signal for FCC2, then the FCC
parameters for FCC2 (at offset 0x8500) must be copied to parameter page 8 (at offset
0x8700).
34.4.8.2.1 MPC8280 Features Unavailable if IDCR is Used
Since their parameter RAM space is used as FCC parameter shadow space, other MPC8280
features associated with this parameter RAM space will not be available. Selection of the
IDCR clock signal must be made with this in mind.
34-50 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
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