Motorola PowerQUICC II MPC8280 Series Reference Manual page 533

burst read access to FPM DRAM (no LOOP) can be modified using this feature. In
this case the configuration registers are defined in the following way.
Machine select UPMA
Port size 64-bit
No write protect (R/W)
Refresh timer value (1024 refresh cycles)
Refresh timer enable
Address multiplex size
Disable timer period
Select between GPL4 and UPMWAIT = UPMWAIT, data sampled at clock
negative edge
Burst inhibit device
The timing diagram in Figure 11-75 shows how the burst-read access shown in
Figure 11-70 can be reduced.
MOTOROLA
Freescale Semiconductor, Inc.
Table 11-43. UPMs Attributes Example
Explanation
Chapter 11. Memory Controller
For More Information On This Product,
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Memory System Interface Example Using UPM
Field
BRx[MS]
BRx[PS]
BRx[WP]
PURT[PURT]
MxMR[RFEN]
MxMR[AMx]
MxMR[DSx]
MxMR[GPL_x4DIS]
ORx[BI]
Value
0b100
0b00
0b0
0x0C
0b1
0b010
0b01
0b1
0b0
11-95