Motorola PowerQUICC II MPC8280 Series Reference Manual page 977

Table 29-18 describes MCCE fields.
Table 29-18. MCCE/MCCM Register Field Descriptions
Bits Name
0 QOV0 QOVx—Receive interrupt queue overflow. IQOV is set (and an interrupt request generated) by the
CP whenever an overflow occurs in the transmit circular interrupt table. This occurs if the CP tries to
1 RINT0
update an interrupt entry that was not handled by the user (such an entry is identified by V = 1).
RINTx—Receive interrupt. When RINT = 1, the MCC generated at least one new entry in the receive
2 QOV1
interrupt circular table. After clearing it, the user reads the next entry from the receive interrupt circular
table and starts processing a specific channel's exception. The user returns from the interrupt handler
3 RINT1
when it reaches a table entry with V = 0.
4 QOV2
5 RINT2
6 QOV3
7 RINT3
8–11 — Reserved, should be cleared.
12 TQOV Transmit interrupt queue overflow. TQOV is set (and interrupt request generated) by the CP
whenever an overflow occurs in the transmit circular interrupt table. This condition occurs if the CP
attempts to write a new interrupt entry into an entry that was not handled by the user. Such an entry
is identified by V = 1.
13 TINT Transmit interrupt. When TINT = 1, at least one new entry in the transmit interrupt circular table was
generated by MCC. After clearing it, the user reads the next entry from the transmit interrupt circular
table and starts processing a specific channel's exception. The user returns from the interrupt handler
when it reaches a table entry with V = 0.
14 GUN Global transmit underrun. This flag indicates whether an underrun occurred inside the MCC's transmit
FIFO array (see Section 29.8.1.2, "Global Transmitter Underrun (GUN)"). The user must clear this bit.
15 GOV Global receiver overrun. This flag indicates whether an overrun occurred inside the MCC's receive
FIFO array (see Section 29.8.1.4, "Global Overrun (GOV)"). The user must clear this bit.
29.8.1.1 Interrupt Circular Table Entry
Each interrupt circular table entry, shown in Figure 29-20, contains information about
channel-specific events. The transmit circular table shows only events caused by
transmission; the receive circular tables shows only events caused by reception. The
corresponding interrupt mask bits are mode-dependent; refer to the appropriate section:
• Section 29.3.1.2 (HDLC mode)
• Section 29.3.2.2 (transparent mode)
• Section 29.3.3.1.1(AAL1 CES mode)
• Section 29.3.4.1 (SS7 mode)
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Freescale Semiconductor, Inc.
Chapter 29. Multi-Channel Controllers (MCCs)
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Description
MCC Exceptions
29-39