Motorola PowerQUICC II MPC8280 Series Reference Manual page 1391

40.7.1 I C Buffer Descriptors (BDs)
2
Receive and transmit buffer descriptors report information about each buffer transferred
and whether a maskable interrupt should be generated. Each 64-bit BD, shown in
Figure 40-13 and Figure 40-14, has the following structure:
• The half word at offset + 0 contains status and control bits. The CP updates the status
bits after the buffer is sent or received.
• The half word at offset + 2 contains the data length (in bytes) that is sent or received.
— For an RxBD, this is the number of octets the CP writes into this RxBD's buffer
once the descriptor closes. The CP updates this field after the received data is
placed into the associated buffer. Memory allocated for this buffer should be no
smaller than MRBLR.
— For a TxBD, this is the number of octets the CP should transmit from its buffer.
Normally, this value should be greater than zero. The CP never modifies this
field.
• The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the pointer must be even and can point to internal or external
memory.
— For a TxBD, the pointer can be even or odd. The buffer can reside in internal or
external memory.
40.7.1.1 I C Receive Buffer Descriptor (RxBD)
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Using RxBDs, the CP reports on each buffer received, closes the current buffer, generates
a maskable interrupt, and starts receiving data in the next buffer when the current one is full.
It closes the buffer when a stop or start condition is found on the I
error occurs. The core should write RxBD bits before the I
0 1 2
Offset + 0 E — W
Offset + 2
Offset + 4
Offset + 6
MOTOROLA
Freescale Semiconductor, Inc.
3 4 5
I L
Data Length
RX Buffer Pointer
Figure 40-13. I
2
Chapter 40. I
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2
The I C Buffer Descriptor (BD) Table
2 C bus or when an overrun
2 C controller is enabled.
—
2
C RxBD
C Controller
13 14 15
OV —
40-13