Motorola PowerQUICC II MPC8280 Series Reference Manual page 701

transfer buffers and the maximum transfer sizes allows longer transfers to memory devices,
optimizes bus usage and thus reduces the overall load on the CP.
For example, 2,016 bytes can be transferred by issuing one
2-Kbyte internal transfer buffer, or by issuing 63
buffer. The load on the CP in the second case is about 63 times more than the first.
19.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)
The IDMA event (status) register (IDSR) is used to report events recognized by the IDMA
controller. On recognition of an event, the controller sets the corresponding IDSR bit. Each
IDMA event bit can generate a maskable interrupt to the core. Even bits are cleared by
writing ones; writing zeros has no effect.
The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables,
and clearing IDMR bits disables, the corresponding interrupts in the event register.
Figure 19-9 shows the bit format for IDSR and IDMR.
0
Field
Reset
R/W
Addr 0x11020 (IDSR1), 0x11028 (IDSR2), 0x11030 (IDSR3), 0x11038 (IDSR4)/
0x11024 (IDMR1), 0x1102C (IDMR2), 0x11034 (IDMR3), 0x1103C (IDMR4)
Figure 19-9. IDMA Event/Mask Registers (IDSR/IDMR)
Table 19-9 describes IDSR/IDMR fields.
Bits Name
0–3 — Reserved, should be cleared.
4 SC Stop completed. Set after the IDMA channel completes processing the
change channel parameters until SC is set.
5 OB Out of buffers. Set to indicate that the IDMA channel encountered no valid BDs for the transfer.
6 EDN External DONE was asserted by device. Set to indicate that the IDMA channel terminated a transfer
because DONE was asserted by an external device, on the former SDMA transaction.
7 BC BD completed. Set only after all data of a BD whose I (interrupt) bit is set has completed transfer to
the destination.
19.8.5 IDMA BDs
Source addresses, destination addresses, and byte counts are presented to the CP using the
special IDMA BDs. The CP reads the BDs, programs the SDMA channel, and notifies the
MOTOROLA
Freescale Semiconductor, Inc.
3
—
R
Table 19-9. IDSR/IDMR Field Descriptions
Chapter 19. SDMA Channels and IDMA Emulation
For More Information On This Product,
Go to: www.freescale.com
_
START
_ commands using a 64-byte
START IDMA
4 5
SC OB
0000_0000
Description
IDMA Operation
command using a
IDMA
6 7
EDN BC
R/W
_ command. Do not
STOP IDMA
19-25