Motorola PowerQUICC II MPC8280 Series Reference Manual page 768

SCC HDLC Features
22.1 SCC HDLC Features
The main features of an SCC in HDLC mode are follows:
• Flexible buffers with multiple buffers per frame
• Separate interrupts for frames and buffers (Rx and Tx)
• Received-frames threshold to reduce interrupt overhead
• Can be used with the SCC DPLL
• Four address comparison registers with mask
• Maintenance of five 16-bit error counters
• Flag/abort/idle generation and detection
• Zero insertion/deletion
• 16- or 32-bit CRC-CCITT generation and checking
• Detection of nonoctet aligned frames
• Detection of frames that are too long
• Programmable flags (0–15) between successive frames
• Automatic retransmission in case of collision
22.2 SCC HDLC Channel Frame Transmission
The HDLC transmitter is designed to work with little or no core intervention. Once enabled
by the core, a transmitter starts sending flags or idles as programmed in the HDLC mode
register (PSMR). The HDLC polls the first BD in the TxBD table. When there is a frame to
transmit, the SCC fetches the data (address, control, and information) from the first buffer
and starts sending the frame after inserting the minimum number of flags specified between
frames. When the end of the current buffer is reached and TxBD[L] (last buffer in frame)
is set, the SCC appends the CRC and closing flag. In HDLC mode, the lsb of each octet and
the msb of the CRC are sent first. Figure 22-1 shows a typical HDLC frame.
Opening Flag Address
8 bits 16 bits
After a closing flag is sent, the SCC updates the frame status bits of the BD and clears
TxBD[R] (buffer ready). At the end of the current buffer, if TxBD[L] is not set (multiple
buffers per frame), only TxBD[R] is cleared. Before the SCC proceeds to the next TxBD in
the table, an interrupt can be issued if TxBD[I] is set. This interrupt programmability allows
the core to intervene after each buffer, after a specific buffer, or after each frame.
The
STOP TRANSMIT
linked buffers or to support efficient error handling. When the SCC receives a
22-2
Freescale Semiconductor, Inc.
Control
8 bits
Figure 22-1. HDLC Framing Structure
command can be used to expedite critical data ahead of previously
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Information (Optional)
8n bits
CRC Closing Flag
16 bits 8 bits
STOP
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