Motorola PowerQUICC II MPC8280 Series Reference Manual page 1114

Transmission Rate Modes—External, Internal, and Expanded Internal
0 1 2
Field PE0 PE1 PE2
Reset
R/W
Addr
16 17 18
Field PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30
Reset
R/W
Addr
Figure 31-64. FCC Transmit Internal Rate Port Enable Register (FIRPERx)
Table 31-51 describes FIRPERx fields.
Table 31-51. FIRPERx Field Descriptions (TIREM=1)
Bit Name
0–15 PEy Port enable
0 Transmit internal rate for PHY address y is disabled. TxClav from this PHY is masked.
1 Transmit Internal rate for PHY address y is enabled. The rate assigned for PHY y is selected by
register FIRSR_HI (refer to Section 31.15.1.6, "FCC Internal Rate Selection Registers
(FIRSR_HI, FIRSR_LO)").
16–30 PEy Port enable.
0 Transmit internal rate for PHY address y is disabled. TxClav from this PHY is masked.
1 Transmit Internal rate for PHY address y is enabled. The rate assigned for PHY y is selected by
register FIRSR_LO (refer to Section 31.15.1.6, "FCC Internal Rate Selection Registers
(FIRSR_HI, FIRSR_LO)").
31 — Reserved, should be cleared.
31.15.1.5 FCC Internal Rate Event Registers (FIRERx)
Transmit internal rate underrun (TIRU) errors are reported for any PHY that has a
transmission deficiency of 8 cells. Under this condition and in internal rate mode only,
FCCE[TIRU] is set, and if the corresponding bit in the FCC mask register (FCCM[TIRU])
is set, an interrupt is generated. If TIREM = 1, the TIRU status per PHY can be read at any
time in the FCC internal rate event register (FIRER). Once FIRER[TIRUy] error status is
set, it can be cleared only by writing 1 to it. To prevent an underrun PHY from continuously
reporting errors, it can be disabled by FIRPER. The sequence of disabling a PHY is as
follows:
• Disable PHY y by clearing FIRPER[y]
• Clear event FIRER[y] by writing 1 to it
• Clear event FCCE[TIRU] by writing 1 to it
31-100
Freescale Semiconductor, Inc.
3 4 5 6
PE3 PE4 PE5 PE6
0000_0000_0000_0000
0x11380 (FIRPER1), 0x113A0 (FIRPER2)
19 20 21 22
0000_0000_0000_0000
0x11382 (FIRPER1), 0x113A2 (FIRPER2)
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7 8 9 10
PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15
R/W
23 24 25 26
R/W
Description
11 12 13 14
27 28 29 30
MOTOROLA
15
31
—