Motorola PowerQUICC II MPC8280 Series Reference Manual page 684

IDMA Transfers
Figure 19-5 shows the IDMA transfer buffer.
Base Address (aligned to buffer size)
Figure 19-5. IDMA Transfer Buffer in the Dual-Port RAM
Each buffer's contents are transferred in three phases:
• First phase. The internal transfer buffer is filled with [EOB
SS_MAX] bytes, read from the source bus. Then, if EOB
EOB
(alignment to source address)
transfer buffer to the destination bus; or if EOB
[EOB
(destination)
size leaves a remainder of 0–31 bytes in the transfer buffer after the last write burst
of the steady-state phase. After the first phase, burst alignment is ensured.
• Steady-state phase. The transfer buffer is filled with SS_MAX bytes (k-1 bursts),
read from the source bus in STS units. Then, SS_MAX bytes are written to the
destination bus, in DTS units, from the transfer buffer. Because alignment is ensured
from first phase, all bus transfers are bursts. This sequence is repeated until there are
no more than SS_MAX bytes to be transferred. A remainder of 0–31 bytes is left in
the transfer buffer after the last burst write.
• Last phase. The remaining data is read into the transfer buffer in bursts, with the last
1–31 bytes read in single accesses. All data in the transfer buffer is written to the
destination bus in bursts, with the last 1–31 bytes written in single accesses. The last
transfers, read/write or both can be accompanied with DONE assertion, if
programmed.
19-8
Freescale Semiconductor, Inc.
EOB[0–31]
128
96
64
32
0
, [EOB
(destination)
+ (k-2)*32] bytes are written bytes are written. This write transfer
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DMA_WRAP determines IDMA transfer buffer size
(32 * k) bytes
SS_MAX
(k-1)*32
(alignment to source address)
(alignment to destination address)
+ SS_MAX] bytes are written from the
> EOB
(destination)
+
≤
,
(source)
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