Motorola PowerQUICC II MPC8280 Series Reference Manual page 1295

Table 35-2. TCMODEx Field Descriptions (continued)
Bits Name
6 SBC Header Single Bit error Correction
0 Perform single bit error correction on the header according to HEC while in Synch mode.
1 Do not perform single bit error correction on the header.
7–8 CF Rx Idle/Unassigned Cells Filtering
00 No cell filtering is done on Rx cells.
01 Idle cell filtering is done - idle cells are discarded.
10 Unassigned cell filtering is done - unassigned cells are discarded.
11 Idle and unassigned cell filtering is done - both idle and unassigned cells are discarded.
The Header of idle cell (ITU-T I.361): b00000000_00000000_00000000_00000001
The Header of unassigned cell (ITU-T I.361): b00000000_00000000_00000000_0000xxx0
Note that physical layer cells bypass the TC layer; they are not filtered. Also note that the filter
works on the header only and ignores the HEC.
9 URE Underrun interrupt (TCER[UR]) enable. Underrun interrupt may be set when Idle cell is
generated by the TC.
0 Underrun interrupt disabled.
1 Underrun interrupt enabled.
10–11 LB Loopback/echo modes
00 Normal operation.
01 Cell echo mode operation. Received cells are transmitted and do not go out to the UTOPIA
bus.
10 Data loopback mode operation. Transmit data stream is connected to the receive data
stream.
11 Not used.
Note that for echo mode operation, TCMODE[SM] should be cleared, independent of the FCC
multi-PHY mode configuration.
12 TBA Tx Byte align
0 Tx data is transferred as soon as it is enabled.
1 Tx data is transferred byte aligned to the Txsyn signal.
13 IMA IMA mode
0 Rx is not in IMA.
1 Rx is in IMA mode.
14 SM Single mode
0 TC is not the only PHY on UTOPIA
1 TC is the only PHY on UTOPIA
15 CM Cell counters mode
0 Reading a cell counter clears the counter.
1 Reading a cell counter does not change the counter's value.
35.4.1.2 Cell Delineation State Machine Registers 1–8 (CDSMRx)
The cell delineation state machine register (CDSMRx), as shown in Figure 35-6, holds the
ALPHA and DELTA parameters of the cell delineation state machine.
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Freescale Semiconductor, Inc.
Chapter 35. ATM Transmission Convergence Layer
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TC Layer Programming Mode
Description
35-9