Motorola PowerQUICC II MPC8280 Series Reference Manual page 1368

Programming the SPI Registers
the order of the string appearing on the line, a byte at a time is:
first nmlk_j__vuts_r
with REV=1,the string has each byte reversed, and the data string image is:
msb nmlk_j__vuts_r
the order of the string appearing on the line, one byte at a time is:
first j_klmn__r_stuv
Example 2
with LEN=7 (data size=8), the following data is selected:
msb ghij_klmn__opqr_stuv
the data string is selected:
msb ghij_klmn__opqr_stuv
with REV=0, the string transmitted, a byte at a time with lsb first is:
first nmlk_jihg__vuts_rqpo
with REV=1, the string is byte reversed and transmitted, a byte at a time, with
lsb first:
first ghij_klmn__opqr_stuv
Example 3
with LEN=0xC (data size=13), the following data is selected:
msb ghij_klmn__xxxr_stuv
the data string selected is:
msb r_stuv__ghij_klmn
with REV=0, the string transmitted, a byte at a time with lsb first is:
first vuts_r__nmlk_jihg
with REV=1, the string is half-word reversed:
msb nmlk_jihg__vuts_r
and transmitted a byte at a time with lsb first:
first ghij_klmn__r_stuv
39.4.2 SPI Event/Mask Registers (SPIE/SPIM)
The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI.
When an event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by
writing a 1—writing 0 has no effect. Setting a bit in the SPI mask register (SPIM) enables
and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared
before the CP clears internal interrupt requests. Figure 39-7 shows both registers.
39-10
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
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Go to: www.freescale.com
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