Motorola PowerQUICC II MPC8280 Series Reference Manual page 1340

HDLC Parameter RAM
The user can configure the HDLC controller not to interrupt the core until a specified
number of frames have been received. This is configured in the received frames threshold
(RFTHR) location of the parameter RAM. This function can be combined with a timer to
implement a time-out if fewer than the threshold number of frames are received.
37.4 HDLC Parameter RAM
When an FCC operates in HDLC mode, the protocol-specific area of the FCC parameter
RAM is mapped with the HDLC-specific parameters in Table 37-1.
Table 37-1. FCC HDLC-Specific Parameter RAM Memory Map
1
Offset Name Width
0x3C — 2 Words Reserved
0x44 C_MASK Word
0x48 C_PRES Word
2
0x4C DISFC Hword Discard frame counter. Counts error-free frames discarded due to lack of buffers.
2
0x4E CRCEC Hword CRC error counter. Counts frames not addressed to the user or frames received in the
2
0x50 ABTSC Hword Abort sequence counter
2
0x52 NMARC Hword Nonmatching address Rx counter. Counts nonmatching addresses received
0x54 MAX_CNT Word
0x58 MFLR Hword Max frame length register. If the HDLC controller detects an incoming HDLC frame
0x5A RFTHR Hword Received frames threshold. Used to reduce the interrupt overhead that might
0x5C RFCNT Hword Received frames count. A decrementing counter used to implement this feature.
37-4
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CRC constant. For the 16-bit CRC-CCITT, initialize C_MASK to 0x0000_F0B8. For
the 32-bit CRC-CCITT, initialize C_MASK to 0xDEBB_20E3.
CRC preset. For the 16-bit CRC-CCITT, initialize C_PRES to 0x0000_FFFF. For the
32-bit CRC-CCITT, initialize C_PRES to 0xFFFF_FFFF.
BSY condition, but does not include overrun, CD lost, or abort errors.
(error-free frames only). See the HMASK and HADDR[1–4] parameter description.
Max_length counter. Temporary decrementing counter that tracks frame length.
that exceeds the user-defined value in MFLR, the rest of the frame is discarded and
the LG (Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC
controller waits for the end of the frame and then reports the frame status and length
in the last RxBD. MFLR includes all in-frame bytes between the opening and closing
flags (address, control, data, and CRC).
otherwise occur when a series of short HDLC frames arrives, each causing an RXF
interrupt. By programming RFTHR, the user lowers the frequency of RXF interrupts,
which occur only when the RFTHR value is reached. Note that the user should provide
enough empty RxBDs to receive the number of frames specified in RFTHR.
Initialize this counter with RFTHR.
MPC8280 PowerQUICC II Family Reference Manual
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