Motorola PowerQUICC II MPC8280 Series Reference Manual page 1297

Table 35-4. TCERx Field Descriptions (continued)
Bits Name
3 MS Misplaced Txsyn signal
Set when Txsyn is out of place. (The first Txsyn is by definition always in place.)
4 PARE Parity event
Set when parity from UTOPIA to transmit is wrong.
5-9 — Reserved
10 ROF Received cell counter overflow
Set when the received cells counter passes its maximum value.
11 TOF Transmitted cell counter overflow
Set when the transmitted cells counter passes its maximum value.
12 EOF Errored cells counter overflow
Set when the errored cells counter passes its maximum value.
13 COF Corrected cells counter overflow
Set when the corrected cells counter passes its maximum value.
14 IOF Tx Idle cells counter overflow
Set when the Tx idle cells counter passes its maximum value.
15 FOF Filtered cells counter overflow
Set when the filtered cells counter passes its maximum value.
35.4.1.4 TC Layer Mask Register (TCMRx)
This register's field description is identical to that of TCER (refer to Section 35.4.1.3, "TC
Layer Event Registers 1–8 (TCERx)"). Each bit that is set in TCMR enables an interrupt
when the corresponding bit in TCER is set.
35.4.2 TC Layer General Registers
The TC layer general registers are registers that are distributed to all of the TC blocks. Each
TC block is represented by specific bits. When accessing a general register each TC block
is responsible for its specific bits only.
35.4.2.1 TC Layer General Event Register (TCGER)
The TC layer general event register (TCGER), as shown in Figure 35-8, summarizes the
events for all the TC blocks. Each bit stands for an ORed event register of a TC block. Once
a bit is set, it indicates that one or more event bits are set in the corresponding TC block
event register.
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 35. ATM Transmission Convergence Layer
For More Information On This Product,
Go to: www.freescale.com
TC Layer Programming Mode
Description
35-11