Motorola PowerQUICC II MPC8280 Series Reference Manual page 1084

ATM Memory Structure
the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a
new command to restart transmission.
ATM TRANSMIT
Figure 31-41 shows the ready bit in the TxBD tables and their associated buffers for two
example ATM channels.
Ch1 TxBD Table
Pointers in the TCT
Ch4 TxBD Table
Pointers in the TCT
Note: The shaded buffers are ready to be sent; unshaded buffers are waiting to be prepared.
Figure 31-41. Transmit Buffers and BD Table Example
31.10.5.2 Receive Buffer Operation
For AAL5 channels, the user should choose to operate in static buffer allocation or in global
buffer allocation by writing to RCT[BUFM]. AAL1 CES and AAL0 channels must use
static buffer allocation.
31.10.5.2.1 Static Buffer Allocation
The user prepares a table of BDs pointing to the receive buffers. The address of the first BD
is put in the channel's RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first
BD in the table and starts filling its associated buffer with received data. When the current
buffer is full, the CP increments RBD_Offset, which is the offset to the current BD from
RBD_BASE, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP
continues receiving. If the BD is not empty, a busy condition has occurred and a busy
interrupt is sent to the event queue.
31-70
Freescale Semiconductor, Inc.
Ch1 TxBD Table
TBD_BASE
0
TBD_Offset
1
1
0
0
Ch4 TxBD Table
TBD_BASE
1
0
0
0
0
TBD_Offset
1
1
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Tx Buffer 1 of Channel 1
BD 1 Tx Buffer 2 of Channel 1
BD 2
Tx Buffer 3 of Channel 1
BD 3
BD 4
Tx Buffer 4 of Channel 1
BD 5
Tx Buffer 5 of Channel 1
Tx Buffer 1 of Channel 4
Tx Buffer 2 of Channel 4
BD 1
BD 2
Tx Buffer 3 of Channel 4
BD 3
BD 4
Tx Buffer 4 of Channel 4
BD 5
Tx Buffer 5 of Channel 4
BD 6
BD 7
Tx Buffer 6 of Channel 4
Tx Buffer 7 of Channel 4
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