Motorola PowerQUICC II MPC8280 Series Reference Manual page 726

SCC Parameter RAM
Table 20-4. SCC Parameter RAM Map for All Protocols (continued)
1
Offset Name Width
0x06 MRBLR Hword Maximum receive buffer length. Defines the maximum number of bytes the MPC8280
0x08 RSTATE Word
0x0C Word
0x10 RBPTR Hword Current RxBD pointer. Points to the current BD being processed or to the next BD the
0x12 Hword Rx internal byte count
0x14 Word
0x18 TSTATE Word
0x1C Word
0x20 TBPTR Hword Current TxBD pointer. Points to the current BD being processed or to the next BD the
0x22 Hword Tx internal byte count
0x24 Word
0x28 RCRC Word
0x2C TCRC Word
0x30
1
From SCC base. See Section 20.3.1, "SCC Base Addresses."
2
These parameters need not be accessed for normal operation but may be helpful for debugging.
3
For CP use only
20-14
Freescale Semiconductor, Inc.
writes to a receive buffer before it goes to the next buffer. The MPC8280 can write fewer
bytes than MRBLR if a condition such as an error or end-of-frame occurs. It never writes
more bytes than the MRBLR value. Therefore, user-supplied buffers should be no
smaller than MRBLR. MRBLR should be greater than zero for all modes. It should be a
multiple of 4 for Ethernet and HDLC modes, and in totally transparent mode unless the
Rx FIFO is 8-bits wide (GSMR_H[RFW] = 1).
Note: Although MRBLR is not intended to be changed while the SCC is operating, it can
be changed dynamically in a single-cycle, 16-bit move (not two 8-bit cycles). Changing
MRBLR has no immediate effect. To guarantee the exact Rx BD on which the change
occurs, change MRBLR only while the receiver is disabled.
Transmit buffer length is programmed in TxBD[Data Length] and is not affected by
MRBLR.
3
Rx internal state
2
Rx internal buffer pointer . The Rx and Tx internal buffer pointers are updated by the
SDMA channels to show the next address in the buffer to be accessed.
receiver uses when it is idling. After reset or when the end of the BD table is reached, the
CPM initializes RBPTR to the value in the RBASE. Although most applications do not
need to write RBPTR, it can be modified when the receiver is disabled or when no Rx
buffer is in use.
2
. The Rx internal byte count is a down-count value initialized with
MRBLR and decremented with each byte written by the supporting SDMA channel.
3
Rx temp
3
Tx internal state
2
Tx internal buffer pointer . The Rx and Tx internal buffer pointers are updated by the
SDMA channels to show the next address in the buffer to be accessed.
transmitter uses when it is idling. After reset or when the end of the BD table is reached,
the CPM initializes TBPTR to the value in the TBASE. Although most applications do not
need to write TBPTR, it can be modified when the transmitter is disabled or when no Tx
buffer is in use (after a
STOP TRANSMIT
and the frame completes its transmission).
2
. A down-count value initialized with TxBD[Data Length] and
decremented with each byte read by the supporting SDMA channel.
3
Tx temp
2
Temp receive CRC
2
Temp transmit CRC
Protocol-specific area. (The size of this area depends on the protocol chosen.)
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Description
or
GRACEFUL STOP TRANSMIT
command is issued
MOTOROLA