Motorola PowerQUICC II MPC8280 Series Reference Manual page 1261

Table summarizes the MPC8280 features that share IDMA parameter space which will not
be available if DREQx is used as IDCR master clock,
Table 34-24. Unavailable Features when DREQx used as IDCR Master Clock
IDCR Master Clock DPRAM Page
DREQ1 8
DREQ2 9
DREQ3 10
DREQ4 11
34.4.8.2.2 Programming the FCC Parameter Shadow
All of the user-defined or user-initialized FCC parameters of the FCC should be copied
from the FCC parameter page to the shadow page. The following parameters are
exceptions:
• RCELL_TMP_BASE of the shadow page must differ from RCELL_TMP_BASE of
the FCC parameter page. This RCELL_TMP_BASE must point to a separate
temporary cell storage area similar to that reserved on the FCC parameter page.
• Either:
— (1) INTT_BASE of the shadow page must differ from the INTT_BASE of the
FCC parameter page, and along with it separate interrupt parameters and queues.
— OR (2) INTT_BASE of the shadow page and FCC parameter page may be the
same and therefore share common structures, but (a) receive interrupts for the
data channels associated with non-IMA links, data channels associated with
non-IDCR IMA links, and ICP channels for group-unassigned IMA links must
be directed to one dedicated interrupt queue, and (b) receive interrupts for the
data channels of group-assigned IMA links using IDCR must be directed to
another dedicated interrupt queue.
• COMM_INFO on the shadow page is unused. ATM commands issued will use the
COMM_INFO fields on the FCC parameter page.
• INT_RCT_BASE and EXT_RCT_BASE should be the same for both the shadow
page and the FCC parameter page. However, (a) received data from data channels
associated with non-IMA links, received data from data channels associated with
non-IDCR IMA links, and received ICP cells from group-unassigned IMA links,
and (b) received data and ICP cells from group-assigned IMA links using IDCR
must never target the same receive queues. This would not normally be done
anyway; however, if it was done, it would result in erratic operation.
MOTOROLA
Freescale Semiconductor, Inc.
MCC1, SMC1, and IDMA1 are unavailable.
MCC2, SMC2, and IDMA2
SPI and IDMA3
RISC Timers, Microcode Rev Num, Random Number Generator
function and IDMA4
Chapter 34. Inverse Multiplexing for ATM (IMA)
For More Information On This Product,
Go to: www.freescale.com
IMA Programming Model
MPC8280 Features Not Available
34-51