Motorola PowerQUICC II MPC8280 Series Reference Manual page 972

MCC Configuration Registers (MCCFx)
Figure 29-16 shows the SI RAM programming for the same overall configuration as the
previous examples, but in this case it does not matter to the application what timeslot of a
superchannel reception begins on. Thus, slot synchronization is not necessary and the
timeslots do not need to be programmed as superchannelled timeslots and the CNT and
BYT fields may be programed normally.
0
MCC LOOP SUPER
1
1
1
1
1
1
1
1
1
The super channel BD tables are associated with channels 1 and 2
Figure 29-16. Receiver Super Channel without Slot Synchronization Example
29.6 MCC Configuration Registers (MCCFx)
The MCC configuration register (MCCF), shown in Figure 29-17, defines the mapping of
the MCC channels to the TDM channels. MCC1 can be connected to SI1 and MCC2 can
be connected to SI2. For each MCCx-SIx pair, each of the four 32 channels subgroups can
be connected to one of the four TDM highways (TDMA, TDMB, TDMC, and TDMD).
0
Field Group 1
Reset
R/W
Addr
Figure 29-17. SI MCC Configuration Register (MCCF)
29-34
Freescale Semiconductor, Inc.
SI RAM
1 2 3–10
MCSEL
SI RAM Address
0 0 0x0
0 0 0x1
0 0 0x2
0 0 0x2
0 0 0x2
0 0 0x5
0 0 0x1
0 0 0x1
0 0 0x8
1 2 3
Group 2
0x11B38 (MCCF1), 0x11B58 (MCCF2)
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11–13 14 15
CNT BYT LST
1 0 Regular Channel
0x0
0x0 1 0 Super Channel 1
1 0 Super Channel 2
0x0
0x0 1 0 Super Channel 2
1 0 Super Channel 2
0x0
0x0 1 0 Regular Channel
1 0 Super Channel 1
0x0
1 0 Super Channel 1
0x0
0x0 1 1 Regular Channel
4 5
Group 3
0000_0000
R/W
6 7
Group 4
MOTOROLA