Motorola PowerQUICC II MPC8280 Series Reference Manual page 1236

IMA Programming Model
Offset Name
0x37 TMP_PCNT
0x38 RXPHYEN
0x3C TXPHYEN
0x40 IMAPHY
0x44 IMAEXTBASE
0x48 IMAGRPT_TX
0x4A IMAGRPT_RX
0x4C IMALINKT_TX
0x4E IMALINKT_RX
0x50 IRLINKSTAT
0x52 TMP_LPTR_RX
0x54 TMP_LPTR_TX
0x56 TMP_GPTR_TX
0x58 TMP_GPORD_TX Hword
0x5A TMP_GPTR_RX
0X5C TMP_RTRN_RX
0x5E TMP_GPTR2_RX Hword
0x60–0x68 IDCR ROOT
PARAMETERS
0x68 —
34-26
Freescale Semiconductor, Inc.
Table 34-3. IMA Root Table
Width
Byte Microcode managed parameter (pass count).
Word Receive PHY enable. Bit array addressed by PHY address (e.g. bit 0
corresponds to PHY 0). Setting a bit enables reception for the
corresponding PHY. Must be used to enable/disable the corresponding
PHY regardless of whether or not the PHY is defined as IMA in IMAPHY.
All cells received by disabled PHYs are discarded. Note that the FCC must
also be enabled in GFMR[ENR] for reception to occur.
Bit 31 is reserved, and must be programmed to zero.
Word Transmit PHY enable. Bit array addressed by PHY address (e.g. bit 0
corresponds to PHY 0). Setting a bit enables transmission for the
corresponding PHY. Must be used to enable/disable the corresponding
PHY regardless of whether or not the PHY is defined as IMA in IMAPHY.
Only idle/unassigned cells are transmitted on disabled PHYs. Note that the
FCC must also be enabled in GFMR[ENT] for transmission to occur.
Bit 31 is reserved, and must be programmed to zero.
Word Bit array addressed by PHY address (e.g. bit 0 corresponds to PHY 0).
Setting a bit defines the corresponding PHY to operate in IMA mode.
Clearing a bit defines the corresponding PHY to operate as a normal
(non-IMA) multi-PHY.
Bit 31 is reserved, and must be programmed to zero.
Word IMA external structure base pointer. Points to region in external memory
where external IMA data structures are located. Must be aligned to a 1MB
boundary (i.e. program bits 12-31 to zero).
Hword Offset of IMA group transmit table in DPRAM. Must be 16-byte aligned.
Hword Offset of IMA group receive table in DPRAM. Must be 64-byte aligned.
Hword Offset of IMA link transmit table in DPRAM. Must be 32-byte aligned.
Hword Offset of IMA link receive table in DPRAM. Must be 32-byte aligned.
Hword Offset of the optional IMA link receive statistics table in DPRAM. Must be
8-byte aligned.
Hword Microcode-managed parameter. Temporary storage of link table pointer.
Hword Microcode-managed parameter. Temporary transmit table pointer.
Hword Microcode-managed parameter. Temporary transmit group pointer.
Microcode-managed parameter. Temporary transmit group order pointer.
Hword Microcode-managed parameter. Temporary receive group pointer.
Hword Microcode-managed parameter. Temporary return pointer.
Microcode-managed parameter. Temporary receive group pointer 2.
— Refer to Section 34.4.8, "IDCR Timer Programming," for more details
— Reserved. Must be programmed to zero during initialization.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
1
(continued)
Description
MOTOROLA