Motorola PowerQUICC II MPC8280 Series Reference Manual page 735

SCCT Data
TINV
Figure 20-14. DPLL Transmitter Block Diagram
The DPLL can be driven by one of the baud rate generator outputs or an external clock,
CLKx. In the block diagrams, this clock is labeled HSRCLK/HSTCLK. The
HSRCLK/HSTCLK should be approximately 8x, 16x, or 32x the data rate, depending on
the coding chosen. The DPLL uses this clock, along with the data stream, to construct a data
clock that can be used as the SCC Rx and/or Tx clock. In all modes, the DPLL uses the input
clock to determine the nominal bit time. If the DPLL is bypassed, HSRCLK/HSTCLK is
used directly as RCLK/TCLK.
At the beginning of operation, the DPLL is in search mode, whereas the first transition
resets the internal DPLL counter and begins DPLL operation. While the counter is
counting, the DPLL watches the incoming data stream for transitions; when one is detected,
the DPLL adjusts the count to produce an output clock that tracks incoming bits.
The DPLL has a carrier-sense signal that indicates when data transfers are on RXD. The
carrier-sense signal asserts as soon as a transition is detected on RXD; it negates after the
programmed number of clocks in GSMR_L[TSNC] when no transitions are detected.
To prevent itself from locking on the wrong edges and to provide fast synchronization, the
DPLL should receive a preamble pattern before it receives the data. In some protocols, the
preceding flags or syncs can function as a preamble; others use the patterns in Table 20-8.
When transmission occurs, the SCC can generate preamble patterns, as programmed in
GSMR_L[TPP, TPL].
MOTOROLA Chapter 20. Serial Communications Controllers (SCCs)
Freescale Semiconductor, Inc.
TENC
TDCR
TEND
DPLL
HSTCLK
Transmitter
Encoded
0
1
S
TENC = NRZI
For More Information On This Product,
Go to: www.freescale.com
SCC Parameter RAM
Divided Clock
HSTCLK
D Q
HSTCLK
CLK
0
1
D
S
HSTCLK
CLK
1x Mode
0
TCLK
1
S
1x Mode
TXEN
TXD
Q
20-23