Motorola PowerQUICC II MPC8280 Series Reference Manual page 1117

Table 31-54 describes FIRSRx_LO fields.
Table 31-54. FIRSRx_LO Field Descriptions (TIREM=1)
Bit Name
0-29 GSy Group select for PHY y
00The transmit internal rate for PHY address y is controlled by FTIRRx_GRP0.
01The transmit internal rate for PHY address y is controlled by FTIRRx_GRP1.
10The transmit internal rate for PHY address y is controlled by FTIRRx_GRP2.
11The transmit internal rate for PHY address y is controlled by FTIRRx_GRP3.
30–31 — Reserved, should be cleared.
31.16 SRTS Generation and Clock Recovery Using
External Logic
The MPC8280 supports SRTS generation using external logic. If SRTS generation is
enabled (TCT[SRT] = 1), the MPC8280 reads SRTS[0–3] from the external SRTS logic and
inserts it into 4 cells whose SN fields equal 1, 3, 5, and 7, as shown in Figure 31-68.
fs
155.52 MHz
Figure 31-68. AAL1 CES SRTS Generation Using External Logic
For every eight cells, the external SRTS logic should supply a valid SRTS code. The CP
reads the SRTS code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte
data size. Each AAL1 CES channel can be programmed to select one of 16 addresses
available for reading the SRTS result. The SRTS code should be placed on the
least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is
synchronized with the sequence count cycle—SRTS[0] is inserted into the cell with SN =
7; SRTS[3] is inserted into the cell with SN = 1. For every eighth AAL1 CES SAR PDU,
the SRTS logic samples a new SRTS and stores it internally. The SRTS is a sample of a 4-bit
counter with a 2.43-MHz reference clock (for E1/T1) synchronized with the network clock.
The MPC8280 supports clock recovery using an external SRTS PLL. If SRTS recovery is
enabled (RCT[SRT]=1), the MPC8280 tracks the SRTS from four incoming cells whose
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
SRTS Generation and Clock Recovery Using External Logic
External SRTS Logic
(N=3008 bits = 8 SAR PDU)
Counter
divided by N
2.43 MHz (E1/T1)
1/64
p = 4 bit counter
For More Information On This Product,
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Description
SRTS
Latch
DMA reads new SRTS code
SN=1 SN=3 SN=5 SN=7
31-103