Motorola PowerQUICC II MPC8280 Series Reference Manual page 1381

When the I 2 C controller is master, the SCL clock output, taken directly from the I
shifts receive data in and transmit data out through SDA. The transmitter arbitrates for the
bus during transmission and aborts if it loses arbitration. When the I
the SCL clock input shifts data in and out through SDA. The SCL frequency can range from
DC to BRGCLK/48.
40.3 I C Controller Transfers
2
To initiate a transfer, the master I
request to an I 2 C slave. The first byte of the message consists of a 7-bit slave port address
and a R/W request bit. Note that because the R/W request follows the slave port address in
the I 2 C bus specification, the R/W request bit must be placed in the lsb (bit 7) unless
operating in reverse data mode; see Section 40.4.1, "I
To write to a slave, the master sends a write request (R/W = 0) along with either the target
slave's address or a general call (broadcast) address of all zeros, followed by the data to be
written. To read from a slave, the master sends a read request (R/W = 1) and the target
slave's address. When the target slave acknowledges the read request, the transfer direction
is reversed, and the master receives the slave's transmit buffer(s). If the receiver (master or
slave) does not acknowledge each byte transfer in the ninth bit frame, the transmitter signals
a transmission error event (I2ER[TXE]). An I
Figure 40-3.
SCL
SDA
Select master or slave mode for the controller using the I
(I2COM[M/S]). Set the master's start bit, I2COM[STR], to begin a transfer; setting a
slave's I2COM[STR] activates the slave to wait for a transfer request from a master.
If a master or slave transmitter's current TxBD[L] is set, transmission stops once the buffer
is sent; that is, I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero,
once the current buffer is sent, the controller begins processing the next TxBD without
waiting for I2COM[STR] to be set again.
The following sections further detail the transfer process.
MOTOROLA
Freescale Semiconductor, Inc.
2
C controller sends a message specifying a read or write
Start Condition
1 2 3 4 5 6
Data Byte
2
Figure 40-3. I C Transfer Timing
2
Chapter 40. I
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2
C Mode Register (I2MOD)."
2 C transfer timing diagram is shown in
Stop Condition
7 8 9
A
C
K
C Controller
2
I C Controller Transfers
2 C BRG,
2 C controller is a slave,
2 C command register
40-3