Motorola MPC8240 Manuals

Manuals and User Guides for Motorola MPC8240. We have 1 Motorola MPC8240 manual available for free PDF download: User Manual

Motorola MPC8240 User Manual

Motorola MPC8240 User Manual (642 pages)

Integrated Host Processor with Integrated PCI

Brand: Motorola | Category: Computer Hardware | Size: 7.5 MB

Table of Contents

Table of Contents

5
Table of Contents

32
- About this Book
  39
  - Overview
    40
  - Address Maps
    41
  - Acronyms and Abbreviations
    44
- Chapter 1 Overview
  
  49
- Chapter 2
  
  72
- Chapter 3 Address Maps
  
  109
- Chapter 5 Powerpc Processor Core
  
  183
  - Overview
    183
    
    MPC8240 Integrated Processor Core Block Diagram
    184
  - Powerpc Processor Core Features
    185
  - Instruction Unit
    187
  - Branch Processing Unit (BPU)
    188
  - Independent Execution Units
    188
  - Instruction Queue and Dispatch Unit
    188
  - Floating-Point Unit (FPU)
    189
  - Integer Unit (IU)
    189
  - Load/Store Unit (LSU)
    189
  - Completion Unit
    190
  - Memory Management Units (Mmus)
    190
  - Memory Subsystem Support
    190
  - System Register Unit (SRU)
    190
  - Cache Units
    191
  - Peripheral Logic Bus Data Transfers
    191
  - Peripheral Logic Bus Interface
    191
  - Peripheral Logic Bus Protocol
    191
  - Peripheral Logic Bus Frequency
    192
  - Programming Model
    192
  - Register Set
    192
  - Powerpc Register Set
    193
    
    MPC8240 Programming Model—Registers
    194
  - Hardware Implementation-Dependent Register 0 (HID0)
    195
  - MPC8240-Specific Registers
    195
  - Hardware Implementation-Dependent Register 1 (HID1)
    198
  - Hardware Implementation-Dependent Register 2 (HID2)
    199
  - Processor Version Register (PVR)
    199
  - Powerpc Instruction Set and Addressing Modes
    200
  - Cache Implementation
    202
    
    Data Cache
    203
    
    Data Cache Organization
    204
    
    Instruction Cache
    205
    
    Cache Coherency
    206
    
    Processor Responses to PCI-To-Memory Transactions
    207
  - Exception Model
    208
  - Exception Classifications for the Processor Core
    210
    
    Exception Priorities
    212
  - Instruction Timing
    214
  - Integer Divide Latency
    215
    
    Differences between the MPC8240 Core and the Powerpc 603E Microprocessor
    216
  - Memory Interface Signal Summary
    221
  - Memory Address Signal Mappings
    223
  - SDRAM Interface Operation
    224
  - SDRAM Data Bus Lane Assignments
    225
    
    Example 512-Mbyte SDRAM Configuration with Parity
    226
- Chapter 6
  
  227
  - Supported SDRAM Organizations
    227
  - SDRAM Address Multiplexing
    228
    
    SDRAM Memory Data Interface
    231
    
    SDRAM Flow-Through Memory Interface
    232
    
    SDRAM Registered Memory Interface
    233
    
    SDRAM Power-On Initialization
    234
    
    MPC8240 Interface Functionality for JEDEC Sdrams
    235
    
    SDRAM Burst and Single-Beat Transactions
    236
    
    SDRAM Page Mode
    237
    
    PGMAX Parameter Setting for SDRAM Interface
    238
    
    SDRAM Paging in Sleep Mode
    239
  - SDRAM Interface Timing Intervals
    240
    
    SDRAM Single-Beat Read Timing (SDRAM Burst Length = 4)
    241
    
    SDRAM Eight-Beat Burst Read Timing Configuration—32-Bit Mode
    242
    
    SDRAM Four-Beat Burst Write Timing—64-Bit Mode
    243
    
    SDRAM Mode-Set Command Timing
    244
    
    RMW Parity Latency Considerations
    245
  - The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 0:31)
    246
    
    SDRAM Registered DIMM Mode
    247
    
    Registered SDRAM DIMM Single-Beat Write Timing
    248
    
    SDRAM Refresh
    249
    
    SDRAM Refresh Timing
    251
  - SDRAM Controller Power Saving Configurations
    252
    
    SDRAM Self Refresh Entry
    253
    
    Processor-To-SDRAM Transaction Examples
    254
    
    PCI-To-SDRAM Transaction Examples
    260
  - FPM or EDO DRAM Interface Operation
    264
    
    Example 16-Mbyte DRAM System with Parity—64-Bit Mode
    265
    
    Supported FPM or EDO DRAM Organizations
    266
  - Unsupported Multiplexed Row and Column Address Bits
    267
    
    FPM or EDO DRAM Address Multiplexing
    268
    
    Column Bit Multiplexing During the Column Phase (CAS)
    269
    
    DRAM Address Multiplexing SDMA[12:0]—32 Bit Mode
    270
    
    DRAM Address Multiplexing SDMA[12:0]—64 Bit Mode
    271
    
    FPM or EDO Memory Data Interface
    272
    
    FPM or EDO DRAM Initialization
    273
    
    FPM or EDO DRAM Interface Timing
    274
  - FPM or EDO Timing Parameters
    275
    
    DRAM Single-Beat Read Timing (no ECC)
    276
    
    DRAM Eight-Beat Burst Read Timing Configuration—32-Bit Mode
    277
    
    DRAM Four-Beat Burst Write Timing (no ECC)—64-Bit Mode
    278
    
    DMA Burst Wrap
    279
    
    RMW Parity Latency Considerations
    280
  - The MPC8240 FPM or EDO ECC Syndrome Encoding (Data Bits 0:31)
    281
    
    FPM or EDO DRAM Interface Timing with ECC
    282
    
    FPM DRAM Burst Read with ECC
    283
    
    FPM or EDO DRAM Refresh
    284
  - FPM or EDO DRAM Power Saving Modes
    285
    
    DRAM Self-Refresh in Sleep Mode
    286
    
    PCI-To-DRAM Transaction Examples
    287
  - Rom/Flash Interface Operation
    291
    
    Mbyte ROM System Including Parity Paths to DRAM—64-Bit Mode
    292
  - Reset Configurations of Rom/Flash Controller
    294
    
    Rom/Flash Address Multiplexing
    295
    
    Or 32-Bit Rom/Flash Interface Timing
    296
    
    Bit Rom/Flash Interface Timing
    299
    
    Bit Rom/Flash Interface—Single-Byte Read Timing
    300
    
    Rom/Flash Interface Write Operations
    301
    
    Rom/Flash Interface Write Timing
    302
    
    Port X Interface
    307
    
    Port X Peripheral Interface Block Diagram
    308
    
    Example of Port X Peripheral Connected to the MPC8240
    309
    
    Example of Port X Peripheral Connected to the MPC8240
    310
    
    Port X Example Write Access Timing
    311
  - PCI Interface Overview
    313
  - Address Maps
    314
    
    The MPC8240 as a PCI Target
    315
    
    PCI Bus Arbitration
    316
    
    Processor-Initiated Transactions to PCI Bus
    317
    
    PCI Bus Arbiter Operation
    318
    
    PCI Bus Parking
    319
    
    Power-Saving Modes and the PCI Arbiter
    320
    
    Basic Transfer Control
    321
  - PCI Bus Commands
    322
    
    Addressing
    323
    
    Memory Space Addressing
    324
    
    Device Selection
    325
    
    Bus Driving and Turnaround
    326
    
    PCI Single-Beat Read Transaction
    327
    
    PCI Write Transactions
    328
    
    Transaction Termination
    329
    
    Target-Initiated Termination
    330
    
    PCI Target-Initiated Terminations
    332
    
    Fast Back-To-Back Transactions
    333
    
    Standard PCI Configuration Header
    334
    
    CONFIG_ADDR Register Format
    336
    
    Type 0 Configuration Translation
    337
    
    Type 0 Configuration—Device Number to IDSEL Translation
    338
    
    Other Bus Transactions
    339
    
    Special-Cycle Transactions
    340
  - Exclusive Access
    341
    
    Completing an Exclusive Access
    342
    
    PCI Parity
    343
  - Error Reporting
    344
  - Initialization Options for PCI Controller
    345
    
    PCI Address Translation Support
    346
    
    Initialization Code Translation in Agent Mode
    347
- Chapter 8
  
  349
  - DMA Overview
    349
  - DMA Register Summary
    350
  - DMA Operation
    351
    
    DMA Direct Mode
    352
    
    DMA Chaining Mode
    353
    
    Periodic DMA Feature
    354
    
    DMA Operation Flow
    355
    
    DMA Coherency
    356
  - DMA Transfer Types
    357
  - Address Map Interactions
    358
    
    Attempted Reads from ROM on the PCI Bus—Host Mode
    359
    
    Attempted Access to ROM on the PCI Bus—Agent Mode
    360
    
    Chaining of DMA Descriptors in Memory
    361
    
    Descriptors in Big-Endian Mode
    362
  - DMA Register Descriptions
    363
    
    DMR Field Descriptions—Offsets 0X100, 0X200
    364
    
    DMA Status Registers (Dsrs)
    366
    
    Current Descriptor Address Registers (Cdars)
    367
    
    Source Address Registers (Sars)
    368
    
    Destination Address Registers (Dars)
    369
    
    DAR and BCR Values—Double PCI Write
    370
    
    Next Descriptor Address Registers (Ndars)
    371
- Chapter 9
  
  373
  - Message Unit (MU) Overview
    373
  - Message and Doorbell Register Programming Model
    374
    
    Message Register Descriptions
    375
    
    Outbound Doorbell Register (ODBR)
    376
    
    PCI Configuration Identification
    377
    
    I 2 O Register Summary
    378
    
    Inbound Fifos
    379
    
    Inbound Free_List FIFO
    380
    
    Outbound Post_List FIFO
    381
    
    Outbound Message Interrupt Mask Register (OMIMR)
    382
    
    Inbound FIFO Queue Port Register (IFQPR)
    383
    
    Outbound FIFO Queue Port Register (OFQPR)
    384
    
    Inbound Message Interrupt Status Register (IMISR)
    385
    
    Inbound Message Interrupt Mask Register (IMIMR)
    386
    
    Inbound Free_Fifo Head Pointer Register (IFHPR)
    387
    
    Inbound Free_Fifo Tail Pointer Register (IFTPR)
    388
    
    Inbound Post_Fifo Tail Pointer Register (IPTPR)
    389
    
    Outbound Free_Fifo Head Pointer Register (OFHPR)
    390
    
    Outbound Post_Fifo Head Pointer Register (OPHPR)
    391
    
    Messaging Unit Control Register (MUCR)
    392
    
    Queue Base Address Register (QBAR)
    393
- Chapter 10
  
  398
  - START Condition
    398
  - Data Transfer
    399
    
    Clock Synchronization
    400
  - Handshaking
    401
    
    I2CADR Field Descriptions—Offset 0X0_3000
    402
  - Serial Bit Clock Frequency Divider Selections
    403
    
    I2CCR Field Descriptions—Offset 0X0_3008
    404
    
    I2CSR Field Descriptions—Offset 0X0_300C
    406
  - Programming Guidelines
    407
  - Initialization Sequence
    408
  - Generation of STOP
    409
  - Slave Mode Interrupt Service Routine
    410
  - EPIC Unit Overview
    413
- Chapter 11
  
  414
  - EPIC Features Summary
    414
  - EPIC Block Diagram
    415
  - EPIC Register Summary
    416
- Chapter 4 Configuration Registers
  
  417
- Chapter 12 Processor Core/Local Memory Buffers
  
  442
- Chapter 13 Error Handling Block Diagram
  
  456
  - Exceptions and Error Signals
    457
    
    PCI Bus Error Signals
    458
    
    Parity Error (PERR)
    459
    
    Processor Interface Errors
    460
    
    Flash Write Error
    461
    
    Memory Read Data Parity Error
    462
    
    Memory Select Error
    463
    
    PCI Data Parity Error
    464
    
    NMI (Nonmaskable Interrupt)
    465
    
    Overview
    467
- Chapter 14 Dynamic Power Management
  
  468
  - Programmable Processor Power Modes
    469
    
    Processor Power Management Modes—Details
    470
    
    Processor Nap Mode
    471
    
    Processor Sleep Mode
    472
    
    Peripheral Logic Power Management
    473
  - Peripheral Logic Power Modes Summary
    474
    
    Peripheral Power Management Modes
    475
    
    PCI Transactions During Nap Mode
    476
    
    System Memory Refresh During Sleep Mode
    477
- Chapter 15
  
  481
- Chapter 16
  
  504
- Chapter 7 PCI Bus Interface
  
  641
  - DMA Controller
    642

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