Motorola PowerQUICC II MPC8280 Series Reference Manual page 1373

Dual-Port RAM
Tx Buffer
Pointer to SPI
TxBD Table
Pointer to SPI
RxBD Table
39.7.1 SPI Buffer Descriptors (BDs)
Receive and transmit BDs report information about each buffer transferred and whether a
maskable interrupt should be generated. Each 64-bit BD, shown in Figure 39-11 and
Figure 39-12, has the following structure:
• The half word at offset + 0 contains status and control bits. The CP updates the status
bits after the buffer is sent or received.
• The half word at offset + 2 contains the data length (in bytes) that is sent or received.
— For an RxBD, this is the number of octets the CP writes into this RxBD's buffer
once the BD closes. The CP updates this field after the received data is placed
into the buffer. Memory allocated for this buffer should be no smaller than
MRBLR.
— For a TxBD, this is the number of octets the CP should transmit from its buffer.
Normally, this value should be greater than zero. If the character length is more
than 8 bits, the data length should be even. For example, to send three characters
of 8-bit data, 1 start, and 1 stop, the data length field should be initialized to 3.
However, to send three characters of 9-bit data, the data length field should be
initialized to 6 since the three 9-bit data fields occupy three half-words in
memory. The CP never modifies this field.
• The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the pointer must be even and can point to internal or external
memory.
— For a TxBD, the pointer can be even or odd, unless the character exceeds 8 bits,
for which it must be even. The buffer can be in internal or external memory.
MOTOROLA
Freescale Semiconductor, Inc.
TxBD Table
Frame Status
Data Length
Buffer Pointer
RxBD Table
Frame Status
Data Length
Buffer Pointer
Figure 39-10. SPI Memory Structure
Chapter 39. Serial Peripheral Interface (SPI)
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The SPI Buffer Descriptor (BD) Table
External Memory
Tx Buffer
Rx Buffer
39-15