Motorola PowerQUICC II MPC8280 Series Reference Manual page 711

Table 19-17. Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1
Important Init Values
DCM[FB] = 0 Not in fly-by mode.
DCM[LP] = 1 Transfers to 60x have low priority; the destination bus is loaded by higher priority devices.
DCM[DMA_WRAP] = 101 The internal buffer is 2,048 bytes long. Transfers from memory on the source bus (PCI) can
be as long as possible (PCI has high arbitration latency and long bursts). Transfers on the
destination side are shorter, as defined in DTS.
DCM[ERM] = 0 IDMA transfers data continuously until a IDMA_STOP command is issued or until the
transfer complete.s DREQ, DONE, and DACK are not connected externally.
DCM[DT] = DC. Do not care. DONE assertion is not defined in memory-to-memory mode.
DCM[S/D] = 00 Memory-to-memory mode.
DCM[SINC] = 1 The source memory address is incremented after transfers.
DCM[DINC] = 1 The destination memory address is incremented after every transfer.
IBASE=IBDPTR= 0x0030 The current BD pointer is set to the BD ring Base address (aligned 16 -bits[3–0]=0000).
DPR_BUF = 0x0800 Initiated to address aligned to 2048 (bits[10–0] = 000_0000_0000).
SS_MAX = 2016(0x07e0) Initiated to (internal buffer size - 32) equal to STS in this mode.
STS = 2016(0x07e0) Transfers from memory on PCI are 2016 bytes long on steady state of work.
DTS = 7*32 (0x00e0) Transfers to memory on 60x are 224 bytes long (7 60x bursts) for steady-state operations.
We have low arbitration priority on the bus (LP = 1) but once we get it we would like to use
it for more that one burst.
every BD[SDTB] = 1 Source memory is on the PCI (multiplexed with local) bus.
every BD[DDTB] = 0 Destination memory is on the 60x bus.
last BD[SDN] = 0 DONE is not asserted on the last transfer from memory on PCI.
last BD[DDN] = 0 DONE is not asserted on the last transfer to memory on the 60x bus.
last BD[L] = 1 IDMA1 is stopped after last BD complete untill
last BD[I]] = 0 IDMA1 set BC interrupt to the core after last BD complete.
IDMR1=0x0f000000 IDMA1 Mask register is programmed to enable all interrupts.
SIMR_L=0x00000800 Interrupt controller is programmed to enable interrupts from IDMA1.
RCCR=0x00200000 IDMA1 configuration: Internal request priority is the lowest.
87FE=0x0100 IDMA1_BASE points to 0x0100 where the parameter table base address is located for
IDMA1.
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 19. SDMA Channels and IDMA Emulation
For More Information On This Product,
Go to: www.freescale.com
IDMA Programming Examples
Description
_ command is reissued.
START IDMA
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