Motorola PowerQUICC II MPC8280 Series Reference Manual page 880

USB Host Description
Bit Name
0 –4 — Reserved, should be cleared.
5 SFT The start-of-frame timer (USSFT[SFT]) wrapped from 11,999 to 0.
6 RESET Reset condition detected. USB reset condition was detected asserted.
7 IDLE IDLE status changed. A change in the status of the serial line was detected. The real time
suspend status is reflected in the USB status register.
8–11 TXEx Tx error. An error occurred during transmission for End Point x (packet not acknowledged or
underrun).
12 SOF Start of frame. A start of frame packet was received. The packet is stored in the FRAME_N
parameter ram entry.
13 BSY Busy condition. Received data has been discarded due to a lack of buffers. This bit is set
after the first character is received for which there is no receive buffer available.
14 TXB Tx buffer. A buffer has been transmitted. This bit is set once the transmit data of the last
character in the buffer was written to the transmit FIFO (if L=0 (last bit)) or after the last
character was transmitted on the line (if L=1).
15 RXB Rx buffer. A buffer has been received. This bit is set after the last character has been written
to the receive buffer and the Rx BD is closed.
27.5.7.6 USB Mask Register (USBMR)
The USBMR is a 16-bit read/write register (0x11B74) that has the same bit formats as the
USB event register. If a bit in the USBMR is one, the corresponding interrupt in the USBER
is enabled. If the bit is zero, the corresponding interrupt in the USBER will be masked. This
register is cleared at reset.
27.5.7.7 USB Status Register (USBS)
The USB status register, described in Figure 27-15 and Table 27-14, is a read-only register
that allows the user to monitor real-time status condition on the USB lines.
0
Field
Reset
R/W
Addr
Table 27-14 describes USBS fields.
27-22
Freescale Semiconductor, Inc.
Table 27-13. USBER Fields
Figure 27-15. USB Status Register (USBS)
MPC8280 PowerQUICC II Family Reference Manual
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Description
—
0000_0000
R
0x11B77
6 7
IDLE
MOTOROLA