Motorola PowerQUICC II MPC8280 Series Reference Manual page 1108

ATM Registers
Table 31-47. FCC ATM Mode Register (FPSMR) (continued)
Bits Name
28 RUMP Receive UTOPIA multiple PHY mode.
0 Receive UTOPIA single PHY mode is selected
1 Receive UTOPIA multiple PHY mode is selected (Use this mode for IMA support
29 HECI HEC included. Used in UDC mode only.
0 HEC octet is not included when UDC mode is enabled.
1 HEC octet is included when UDC mode is enabled.
30 HECC Receive HEC check
0 Do not check Rx HEC
1 Check Rx HEC. HEC errors are reported in UTOPIAE counter (see Section 31.10.7, "UNI
Statistics Table"). This option can be used only in UTIPIA 8-bit data bus size.
31 COS Coset mode enable
0 Check Rx HEC with no COSET
1 Check Rx HEC with COSET mode enabled
1
MPC8264 and MPC8266
31.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)
The FCCE register is the ATM controller event register when the FCC operates in ATM
mode. When it recognizes an event, the ATM controller sets the corresponding FCCE bit.
Interrupts generated by this register can be masked in FCCM. FCCE is memory-mapped
and can be read at any time. Bits are cleared by writing ones to them; writing zeros has no
effect. Unmasked bits must be cleared before the CP clears the internal interrupt request.
FCCM is the ATM controller mask register. The FCCM has the same bit format as FCCE.
Setting an FCCM bit enables and clearing a bit masks the corresponding interrupt in the
FCCE.
0 4
Field —
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
Figure 31-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM)
31-94
Freescale Semiconductor, Inc.
only.
5 6 7 8
TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0
0000_0000_0000_0000
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)
0000_0000_0000_0000
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
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Description
9 10 11 12
R/W
—
R/W
1
)
13 14 15
31
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