Motorola PowerQUICC II MPC8280 Series Reference Manual page 1091

Offset Bits Name
0x00 0 E
1 —
2 W
3 I
4 SNE
5 —
6 CM
7–15 —
0x02 — DL
0x04 — RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in
31.10.5.6 AAL0 RxBD
Figure 31-48 shows the AAL0 RxBD.
0 1
Offset + 0x00 E —
Offset + 0x02
Offset + 0x04
Offset + 0x06
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Table 31-36. AAL1 RxBD Field Descriptions
Empty
0 The buffer associated with this RxBD is filled with received data or data reception was
aborted due to an error. The core can read or write any fields of this RxBD. The CP
cannot use this BD again while E = 0.
1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP.
Once E is set, the core should not write any fields of this RxBD.
Reserved, should be cleared.
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer is used,
the CP receives incoming data into the first BD in the table. The number of RxBDs in
this table is programmable and is determined only by the W bit. The current table
overall space is constrained to 64 Kbytes.
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this
buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold.
Sequence number error. SNE is set when a sequence number error is detected in the
current AAL1 CES buffer.
Reserved, should be cleared.
Continuous mode
0 Normal operation.
1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the
associated buffer to be overwritten automatically when the CP next accesses this BD.
Reserved, should be cleared.
Data length. The number of octets the CP writes into the buffer once its BD is closed.
either internal or external memory. It is recommended that the pointer be burst-aligned.
2 3 4 5
W I — CM
Data Length (DL)/Channel Code (CC)
Rx Data Buffer Pointer (RXDBPTR)
Figure 31-48. AAL0 RxBD
For More Information On This Product,
Go to: www.freescale.com
Description
6 7 9 10
— CRE OAM
ATM Memory Structure
11 12 15
—
31-77