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Motorola MC68020 User Manual

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MC68020
MC68EC020
MICROPROCESSORS
USER'S MANUAL
First Edition
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
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Motorola was negligent regarding the design or manufacture of the part. Motorola and the
are registered trademarks of Motorola, Inc. Motorola, Inc. is an
Equal Opportunity/Affirmative Action Employer.
© MOTOROLA INC., 1992

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  Summary of Contents for Motorola MC68020

  • Page 1 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.
  • Page 2: Introduction

    MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32- bit, second-generation, enhanced embedded microprocessor. Throughout this manual, “MC68020/EC020” is used when information applies to both the MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when information applies only to the MC68020 or MC68EC020, respectively.
  • Page 3: Table Of Contents

    Section 3 Signal Description Signal Index .................... 3-2 Function Code Signals (FC2–FC0) ............3-2 Address Bus (A31–A0, MC68020)(A23–A0, MC68EC020) ....3-2 Data Bus (D31–D0) ................. 3-2 Transfer Size Signals (SIZ1, SIZ0) ............3-2 Asynchronous Bus Control Signals ............3-4 Interrupt Control Signals................3-5 Bus Arbitration Control Signals ...............
  • Page 4 5.4.1.2 Autovector Interrupt Acknowledge Cycle ......... 5-48 5.4.1.3 Spurious Interrupt Cycle ..............5-48 5.4.2 Breakpoint Acknowledge Cycle ............5-50 5.4.3 Coprocessor Communication Cycles ..........5-53 Bus Exception Control Cycles..............5-53 5.5.1 Bus Errors ................... 5-55 viii M68020 USER’S MANUAL MOTOROLA...
  • Page 5 MC68020 Bus Arbitration ..............5-63 5.7.1.1 Bus Request (MC68020) ..............5-66 5.7.1.2 Bus Grant (MC68020) ..............5-66 5.7.1.3 Bus Grant Acknowledge (MC68020) ..........5-66 5.7.1.4 Bus Arbitration Control (MC68020) ..........5-67 5.7.2 MC68EC020 Bus Arbitration ............... 5-70 5.7.2.1 Bus Request (MC68EC020) ............5-71 5.7.2.2...
  • Page 6 7.2.3.3 Coprocessor Context Save Instruction ..........7-20 7.2.3.3.1 Format ..................7-20 7.2.3.3.2 Protocol ..................7-21 7.2.3.4 Coprocessor Context Restore Instruction ........7-22 7.2.3.4.1 Format ..................7-22 7.2.3.4.2 Protocol ..................7-23 Coprocessor Interface Register Set ............7-24 M68020 USER’S MANUAL MOTOROLA...
  • Page 7 Coprocessor-Detected Illegal Command or Condition Words ..7-51 7.5.1.3 Coprocessor Data-Processing-Related Exceptions ......7-51 7.5.1.4 Coprocessor System-Related Exceptions ........7-51 7.5.1.5 Format Errors ................... 7-52 7.5.2 Main-Processor-Detected Exceptions ..........7-52 7.5.2.1 Protocol Violations ................7-52 7.5.2.2 F-Line Emulator Exceptions ............. 7-54 MOTOROLA M68020 USER’S MANUAL...
  • Page 8 Control Instructions................8-38 8.2.17 Exception-Related Instructions ............8-39 8.2.18 Save and Restore Operations ............. 8-40 Section 9 Applications Information Floating-Point Units ................. 9-1 Byte Select Logic for the MC68020/EC020..........9-5 Power and Ground Considerations ............9-9 M68020 USER’S MANUAL MOTOROLA...
  • Page 9 Standard MC68020 Ordering Information.......... 11-1 11.1.2 Standard MC68EC020 Ordering Information ........11-1 11.2 Pin Assignments and Package Dimensions .......... 11-2 11.2.1 MC68020 RC and RP Suffix—Pin Assignment ......... 11-2 11.2.2 MC68020 RC Suffix—Package Dimensions ........11-3 11.2.3 MC68020 RP Suffix—Package Dimensions........11-4 11.2.4 MC68020 FC and FE Suffix—Pin Assignment ........
  • Page 10 Relationship between External and Internal Signals........5-2 Input Sample Window ..................5-2 Internal Operand Representation ..............5-6 MC68020/EC020 Interface to Various Port Sizes ..........5-6 Long-Word Operand Write to Word Port Example........... 5-10 Long-Word Operand Write to Word Port Timing ..........5-11 Word Operand Write to Byte Port Example .............
  • Page 11 Halt Operation Timing ..................5-61 5-42 MC68020 Bus Arbitration Flowchart for Single Request ........5-64 5-43 MC68020 Bus Arbitration Operation Timing for Single Request ...... 5-65 5-44 MC68020 Bus Arbitration State Diagram ............5-67 5-45 MC68020 Bus Arbitration Operation Timing—Bus Inactive ......5-69 5-46 MC68EC020 Bus Arbitration Flowchart for Single Request ......
  • Page 12 Page Number Title Number Coprocessor Address Map in MC68020/EC020 CPU Space ......7-7 Coprocessor Interface Register Set Map ............7-7 Coprocessor General Instruction Format (cpGEN) .......... 7-8 Coprocessor Interface Protocol for General Category Instructions....7-10 Coprocessor Interface Protocol for Conditional Category Instructions .... 7-11 Branch on Coprocessor Condition Instruction Format (cpBcc.W) ....
  • Page 13 Chip Select Generation PAL ................9-3 Chip Select PAL Equations ................9-4 Bus Cycle Timing Diagram ................9-4 Example MC68020/EC020 Byte Select PAL System Configuration ....9-7 MC68020/EC020 Byte Select PAL Equations ..........9-8 High-Resolution Clock Controller ..............9-11 Alternate Clock Solution ................... 9-11 Access Time Computation Diagram ..............
  • Page 14 SIZ1, SIZ0 Signal Encoding ................5-7 Address Offset Encodings ................5-7 Data Bus Requirements for Read Cycles ............5-8 MC68020/EC020 Internal to External Data Bus Multiplexer— Write Cycles ....................5-9 Memory Alignment and Port Size Influence on Read/Write Bus Cycles ..5-20 Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports .....
  • Page 15 AVDV Less Than or Equal to the CPU Maximum Frequency Rating......9-14 Access Status Register Codes................. 9-18 θ 10-1 vs. Airflow—MC68020 CQFP Package ........... 10-3 10-2 Power vs. Rated Frequency (at T Maximum = 110°C) ......... 10-3 10-3 Temperature Rise of Board vs. P —MC68020 CQFP Package ....
  • Page 16: Section 1: Overview Um Rev

    9/29/95 SECTION 1: OVERVIEW UM Rev.1.0 M68020 USER’S MANUAL MOTOROLA...
  • Page 17 MC68020/EC020 ACRONYM LIST BCD — Binary-Coded Decimal CAAR — Cache Address Register CACR — Cache Control Register CCR — Condition Code Register CIR — Coprocessor Interface Register CMOS — Complementary Metal Oxide Semiconductor CPU — Central Processing Unit CQFP — Ceramic Quad Flat Pack DDMA —...
  • Page 18 The MC68EC020 is an economical high-performance embedded microprocessor based on the MC68020 and has been designed specifically to suit the needs of the embedded microprocessor market. The major differences in the MC68EC020 and the MC68020 are that the MC68EC020 has a 24-bit address bus and does not implement the following signals: ECS , OCS , DBEN , IPEND , and BGACK .
  • Page 19: Features

    • 4-Gbyte Direct Addressing Range for the MC68020 • 16-Mbyte Direct Addressing Range for the MC68EC020 • Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz • Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz A block diagram of the MC68020/EC020 is shown in Figure 1-1.
  • Page 20: Mc68020/Ec020 Block Diagram

    ADDRESS SIZE ADDRESS COUNTER SECTION SECTION MULTIPLEXER PADS SECTION ADDRESS MISALIGNMENT MULTIPLEXER BUS CONTROLLER WRITE PENDING PREFETCH PENDING BUFFER BUFFER MICROBUS CONTROL LOGIC BUS CONTROL SIGNALS 24-Bit for MC68EC020 Figure 1-1. MC68020/EC020 Block Diagram MOTOROLA M68020 USER’S MANUAL 1- 3...
  • Page 21: Programming Model

    1.2 PROGRAMMING MODEL The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level use the registers of the user model.
  • Page 22 DATA REGISTERS ADDRESS REGISTERS USER STACK A7 (USP) POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 1-2. User Programming Model MOTOROLA M68020 USER’S MANUAL 1- 5...
  • Page 23: Supervisor Programming Model Supplement

    INTERRUPT STACK A7' (ISP) POINTER MASTER STACK A7'' (MSP) POINTER STATUS (CCR) REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS CACHE CONTROL CACR REGISTER CACHE ADDRESS CAAR REGISTER Figure 1-3. Supervisor Programming Model Supplement 1- 6 M68020 USER’S MANUAL MOTOROLA...
  • Page 24: Status Register (Sr)

    The alternate function code registers, SFC and DFC, contain 3-bit function codes. For the MC68020, function codes can be considered extensions of the 32-bit linear address that optionally provide as many as eight 4-Gbyte address spaces; for the MC68EC020, function codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces.
  • Page 25: Data Types And Addressing Modes Overview

    6. Long-Word Integers (32 bits) 7. Quad-Word Integers (64 bits) In addition, the MC68020/EC020 instruction set supports operations on other data types such as memory addresses. The coprocessor mechanism allows direct support of floating- point operations with the MC68881 and MC68882 floating-point coprocessors as well as specialized user-defined data types and functions.
  • Page 26 16 or 32 bits. Program Counter <data> = Immediate value of 8, 16, or 32 bits ( ) = Effective Address Use as indirect access to long-word address. MOTOROLA M68020 USER’S MANUAL 1- 9...
  • Page 27: Instruction Set Overview

    18 addressing modes. 1.5 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS The full addressing range of the MC68020 is 4 Gbytes (4,294,967,296 bytes) in each of eight address spaces; the full addressing range of the MC68EC020 is 16 Mbytes (16,777,216 bytes) in each of the eight address spaces.
  • Page 28 MOVE Move cpRESTORE Restore Internal State of Coprocessor MOVEA Move Address cpSAVE Save Internal State of Coprocessor MOVE CCR Move Condition Code Register cpScc Set Conditionally MOVE SR Move Status Register cpTRAPcc Trap Conditionally MOTOROLA M68020 USER’S MANUAL 1- 11...
  • Page 29: Virtual Machine

    (and should be emulated) are trapped to the governing operating system and performed by its software. In the MC68020/EC020 implementation of a virtual machine, the virtual application runs at the user privilege level. The governing operating system executes at the supervisor...
  • Page 30: Cache Memory

    Additionally, instructions that reside in proximity to the instructions currently in use also have a high probability of being utilized within a short period. To exploit these locality characteristics, the MC68020/EC020 contains an on-chip instruction cache.
  • Page 31: Processing States

    For example, if during the exception processing of one bus error another bus error occurs, the MC68020/EC020 has not completed the transition to normal processing and has not completed saving the internal state of the machine; therefore, the processor assumes that the system is not operational and halts.
  • Page 32: Privilege Levels

    ISP, can be used for interrupt control information and workspace area as interrupt handling routines require. When the M-bit is clear, the MC68020/EC020 is in the interrupt mode of the supervisor privilege level, and operation is the same as supervisor mode in the MC68000, MC68HC001, MC68008, and MC68010.
  • Page 33: User Privilege Level

    After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space. The RTE instruction returns to the program that was executing when the exception occurred. It restores the exception stack frame saved on the supervisor stack. If the frame MOTOROLA M68020 USER’S MANUAL 2- 3...
  • Page 34: Address Space Types

    Table 2-1 lists the types of accesses defined for the MC68020/EC020 and the corresponding values of the FC2–FC0 signals. Table 2-1. Address Space Encodings...
  • Page 35: Exception Processing

    Details of exception processing are provided in Section 6 Exception Processing, and Table 6-1 lists the exception vector assignments. MOTOROLA M68020 USER’S MANUAL 2- 5...
  • Page 36: Exception Stack Frame

    Processing for a complete list of exception stack frames. STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET ADDITIONAL PROCESSOR STATE INFORMATION (2, 6, 12, OR 42 WORDS, IF NEEDED) Figure 2-1. General Exception Stack Frame 2- 6 M68020 USER’S MANUAL MOTOROLA...
  • Page 37: Signal Description

    ADDRESS BUS A31–A0 IPL2 INTERRU CONTRO DATA BUS D31–D0 IPEND SIZ0 AVEC TRANSFER SIZE SIZ1 BUS ARB CONTRO BGACK MC68020 RESET HALT BUS EXC ASYNCHRONOUS CONTRO BUS CONTROL BERR DBEN DSACK0 DSACK1 CDIS EMULATOR SUPPORT Figure 3-1. Functional Signal Groups MOTOROLA M68020 USER’S MANUAL...
  • Page 38: Signal Index

    These three-state bidirectional signals provide the general-purpose data path between the MC68020/EC020 and all other devices. The data bus can transfer 8, 16, 24, or 32 bits of data per bus cycle. D31 is the most significant bit of the data bus. Refer to Section 5 Bus Operation for more information on the data bus and its relationship to bus operation.
  • Page 39: Signal Index

    Statically disables the on-chip cache to assist emulator support. Clock Clock input to the processor. Power Supply Power supply. Ground Ground connection. This signal is implemented in the MC68020 and not implemented in the MC68EC020. MOTOROLA M68020 USER’S MANUAL 3- 3...
  • Page 40: Asynchronous Bus Control Signals

    During a write cycle, DS indicates that the MC68020/EC020 has placed valid data on the bus. During two-clock synchronous write cycles, the MC68020/EC020 does not assert DS . Refer to Section 5 Bus Operation for more information about the relationship of DS to bus operation.
  • Page 41: Interrupt Control Signals

    Operation for more information on these signals and their relationship to dynamic bus sizing. 3.7 INTERRUPT CONTROL SIGNALS The following signals are the interrupt control signals for the MC68020/EC020. Note that IPEND is implemented in the MC68020 and not implemented in the MC68EC020. Interrupt Priority Level Signals (IPL2–IPL0) These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry.
  • Page 42: Bus Arbitration Control Signals

    3.8 BUS ARBITRATION CONTROL SIGNALS The following signals are the bus arbitration control signals used to determine which device in a system is the bus master. Note that BGACK is implemented in the MC68020 and not implemented in the MC68EC020.
  • Page 43: Emulator Support Signal

    CDIS is negated. 3.11 CLOCK (CLK) The CLK signal is the clock input to the MC68020/EC020. This TTL-compatible signal should not be gated off at any time while power is applied to the processor. Refer to Section 9 Applications Information for suggestions on clock generation. Refer to Section 10 Electrical Characteristics for electrical characteristics.
  • Page 44: Signal Summary

    3.13 SIGNAL SUMMARY Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk (*) are implemented in the MC68020 and not implemented in the MC68EC020. Table 3-2. Signal Summary...
  • Page 45: On-Chip Cache Memory

    SECTION 4 ON-CHIP CACHE MEMORY The MC68020/EC020 incorporates an on-chip cache memory as a means of improving performance. The cache is implemented as a CPU instruction cache and is used to store the instruction stream prefetch accesses from the main memory.
  • Page 46: Mc68020/Ec020 On-Chip Cache Organization

    COMPARATOR LINE Figure 4-1. MC68020/EC020 On-Chip Cache Organization When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the word required is in the cache. This check is achieved by first using the index field (A7–A2) of the access address as an index into the on-chip cache.
  • Page 47: Cache Reset

    CACR are also cleared. 4.3 CACHE CONTROL Only the MC68020/EC020 cache control circuitry can directly access the cache array, but a supervisor program can set bits in the CACR to exercise control over cache operations. The supervisor level also has access to the CAAR, which contains the address for a cache entry to be cleared.
  • Page 48: Cache Address Register (Caar)

    RESERVED Figure 4-3. Cache Address Register Bits 31–8, 1, and 0—Reserved These bits are reserved for use by Motorola. Index Field The index field contains the address for the “clear cache entry” operations. The bits of this field, which correspond to A7–A2, specify the index and a long word of a cache line.
  • Page 49: Bus Operation

    MC68020/EC020 clock, introducing a delay. This delay is the time period required for the MC68020/EC020 to sample an input signal, synchronize the input to the internal clocks of the processor, and determine whether the MOTOROLA M68020 USER’S MANUAL...
  • Page 50: Bus Control Signals

    The MC68020/EC020 initiates a bus cycle by driving the A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W outputs. However, if the MC68020/EC020 finds the required instruction in the on- chip cache, the processor aborts the cycle before asserting the AS.The assertion of AS ensures that the cycle has not been aborted by these internal conditions.
  • Page 51: Address Bus

    When initiating a bus cycle, the MC68020 asserts ECS in addition to A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W . ECS can be used to initiate various timing sequences that are eventually qualified with AS. Qualification with AS may be required since, in the case of an internal cache hit, a bus cycle may be aborted after ECS has been asserted.
  • Page 52: Data Strobe

    AS during a write cycle. 5.1.6 Data Buffer Enable The MC68020 DBEN signal is used to enable external data buffers while data is present on the data bus. During a read operation, DBEN is asserted one clock cycle after the beginning of the bus cycle and is negated as DS is negated.
  • Page 53: Data Transfer Mechanism

    (Refer to 5.2.2 Misaligned Operands for the case of a word or byte address.) If the port responds that it is 32 bits wide, the MC68020/EC020 latches all 32 bits of data and continues with the next operation. If the port responds that it is 16 bits wide, the MC68020/EC020 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits.
  • Page 54: Internal Operand Representation

    BYTE OPERAND Figure 5-3. Internal Operand Representation Figure 5-4 shows the required organization of data ports on the MC68020/EC020 bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 5-4 are connected through the internal data bus and data multiplexer to the external data bus. This path is the means through which the MC68020/EC020 supports dynamic bus sizing and operand misalignment.
  • Page 55: Siz1, Siz0 Signal Encoding

    A1–A0 also affect operation of the data multiplexer. During an operand transfer, A31–A2 (for the MC68020) or A23–A2 (for the MC68EC020) indicate the long-word base address of that portion of the operand to be accessed; A1 and A0 indicate the byte offset from the base.
  • Page 56: Data Bus Requirements For Read Cycles

    Byte Port Long-Word Port Word Port Transfer External Size Address External Data Bytes External Data Bytes Size Data Bytes Required Required Required SIZ1 SIZ0 D31–D24 D23–D16 D15–D8 D7–D0 D31–D24 D23–D16 D31–D24 Byte Word 3 Bytes Long Word M68020 USER’S MANUAL MOTOROLA...
  • Page 57 Table 5-5 lists the combinations of SIZ1, SIZ0, A1, and A0 and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68020/EC020 to the external data bus. Table 5-5. MC68020/EC020 Internal to External Data Bus Multiplexer—Write Cycles...
  • Page 58: Long-Word Operand Write To Word Port Example

    Figure 5-5 shows the transfer (write) of a long-word operand to a word port. In the first bus cycle, the MC68020/EC020 places the four operand bytes on the external bus. Since the address is long-word aligned in this example, the multiplexer follows the pattern in the entry of Table 5-5 corresponding to SIZ0, SIZ1, A0, A1 = 0000.
  • Page 59: Long-Word Operand Write To Word Port Timing

    DBEN D31–D24 D23–D16 WORD WRITE WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-6. Long-Word Operand Write to Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 11...
  • Page 60: Word Operand Write To Byte Port Example

    Figure 5-8 shows the associated bus transfer signal timing. WORD OPERAND D31 DATA BUS D24 BYTE MEMORY MC68020/EC020 MEMORY CONTROL SIZ1 SIZ0 A1 DSACK1 DSACK0 Figure 5-7. Word Operand Write to Byte Port Example 5-12 M68020 USER’S MANUAL...
  • Page 61: Word Operand Write To Byte Port Timing

    DSACK0 DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE BYTE WRITE WORD OPERAND WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-8. Word Operand Write to Byte Port Timing MOTOROLA M68020 USER’S MANUAL 5- 13...
  • Page 62: Misaligned Operands

    MC68000, MC68008, and MC68010 implementations allow long-word transfers on odd- word boundaries but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. Although the MC68020/EC020 does not enforce any alignment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned.
  • Page 63: Misaligned Long-Word Operand Write To Word Port Timing

    D23–D16 D15–D8 D7–D0 BYTE WRITE WORD WRITE BYTE WRITE LONG-WORD OPERAND WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-10. Misaligned Long-Word Operand Write to Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 15...
  • Page 64: Misaligned Word Operand Write To Word Port Example

    LONG-WORD OPERAND (REGISTER) DATA BUS MEMORY CONTROL WORD MEMORY MC68020/EC020 SIZ1 SIZ0 A2 DSACK1 DSACK0 Figure 5-11. Misaligned Long-Word Operand Read from Word Port Example Figures 5-12 and 5-13 show a word transfer (write) to an odd address in word-organized memory.
  • Page 65: Misaligned Word Operand Write To Word Port Timing

    WORD WRITE BYTE WRITE WORD OPERAND WRITE TO A1, A0 = 01 For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-13. Misaligned Word Operand Write to Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 17...
  • Page 66: Misaligned Word Operand Read From Word Bus Example

    WORD OPERAND (REGISTER) DATA BUS WORD MEMORY MC68020/EC020 MEMORY CONTROL SIZ1 SIZ0 A2 DSACK1 DSACK0 Figure 5-14. Misaligned Word Operand Read from Word Bus Example Figures 5-15 and 5-16 show an example of a long-word transfer (write) to an odd address in long-word-organized memory.
  • Page 67 DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE 3-BYTE WRITE LONG-WORD OPERAND WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-16. Misaligned Long-Word Operand Write to Long-Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 19...
  • Page 68: Effects Of Dynamic Bus Sizing And Operand Misalignment

    Instruction prefetches are always two words from a long-word boundary Table 5-6 reveals that bus cycle throughput is significantly affected by port size and alignment. The MC68020/EC020 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications.
  • Page 69: Address, Size, And Data Bus Relationships

    A dash (—) implies that the byte enable signal does not apply. The MC68020/EC020 always drives all sections of the data bus because, at the beginning of a write cycle, the bus controller does not know the port size.
  • Page 70: Cache Interactions

    AS is not asserted. For the MC68020, if the bus is not occupied with another read or write cycle, the bus controller asserts the ECS signal (and the OCS signal, if appropriate). It is possible to have ECS asserted on multiple consecutive clock cycles.
  • Page 71: Byte Enable Signal Generation For 16- And 32-Bit Ports

    UPPER MIDDLE DATA (32-BIT PORT) LOWER MIDDLE DATA (32-BIT PORT) SIZ1 LOWER LOWER DATA (32-BIT PORT) UPPER DATA (16-BIT PORT) LOWER DATA (16-BIT PORT) Figure 5-18. Byte Enable Signal Generation for 16- and 32-Bit Ports MOTOROLA M68020 USER’S MANUAL 5- 23...
  • Page 72: Bus Operation

    5.2.6 Bus Operation The MC68020/EC020 bus is used in an asynchronous manner allowing external devices to operate at clock frequencies different from the MC68020/EC020 clock. Bus operation uses the handshake lines (AS, DS, DSACK0, DSACK1, BERR, and HALT) to control data transfers.
  • Page 73: Data Transfer Cycles

    In addition, the bus master is responsible for de-skewing DSACK1/DSACK0, D31–D0, BERR, HALT, and, for the MC68020, DBEN from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations.
  • Page 74: Read Cycle

    During a read cycle, the processor receives data from a memory, coprocessor, or peripheral device. If the instruction specifies a long-word operation, the MC68020/EC020 attempts to read four bytes at once. For a word operation, it attempts to read two bytes at once and for a byte operation, one byte.
  • Page 75: Byte Read Cycle Flowchart

    3) NEGATE DBEN TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE DSACK1/DSACK0 START NEXT CYCLE This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-20. Byte Read Cycle Flowchart MOTOROLA M68020 USER’S MANUAL 5- 27...
  • Page 76: Byte And Word Read Cycles—32-Bit Port

    A31–A2 FC2–FC0 SIZ1 WORD BYTE SIZ0 DSACK1 DSACK0 DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD READ BYTE READ BYTE READ Figure 5-21. Byte and Word Read Cycles—32-Bit Port 5-28 M68020 USER’S MANUAL MOTOROLA...
  • Page 77: Long-Word Read—8-Bit Port

    D23–D16 D15–D8 D7–D0 BYTE READ BYTE READ BYTE READ BYTE READ LONG-WORD OPERAND READ FROM 8-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-22. Long-Word Read—8-Bit Port MOTOROLA M68020 USER’S MANUAL 5- 29...
  • Page 78: Long-Word Read—16- And 32-Bit Ports

    D7–D0 LONG-WORD READ WORD READ WORD READ FROM 32-BIT PORT LONG-WORD OPERAND READ FROM 16-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-23. Long-Word Read—16- and 32-Bit Ports 5-30 M68020 USER’S MANUAL MOTOROLA...
  • Page 79 State 0 MC68020—The read cycle starts in state 0 (S0). The processor asserts ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a read operation, OCS is asserted simultaneously. During S0, the processor places a valid address on A31–A0 and valid function codes on FC2–FC0.
  • Page 80 MC68020/EC020—At the end of state 4 (S4), the processor latches the incoming data. State 5 MC68020—The processor negates AS, DS, and DBEN during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems. R/W, SIZ1–...
  • Page 81: Write Cycle

    1) NEGATE AS AND DS 2) REMOVE DATA FROM D31–D0 TERMINATE CYCLE 3) NEGATE DBEN 1) NEGATE DSACK1/DSACK0 START NEXT CYCLE This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-24. Write Cycle Flowchart MOTOROLA M68020 USER’S MANUAL 5- 33...
  • Page 82: Read-Write-Read Cycles—32-Bit Port

    A31–A2 FC2–FC0 SIZ1 LONG WORD SIZ0 DSACK1 DSACK0 DBEN D31–D0 BYTE READ WRITE WRITE READ WITH WAIT STATES For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-25. Read-Write-Read Cycles—32-Bit Port 5-34 M68020 USER’S MANUAL MOTOROLA...
  • Page 83: Byte And Word Write Cycles—32-Bit Port

    SIZ0 DSACK1 DSACK0 DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD WRITE BYTE WRITE BYTE WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-26. Byte and Word Write Cycles—32-Bit Port MOTOROLA M68020 USER’S MANUAL 5- 35...
  • Page 84: Long-Word Operand Write—8-Bit Port

    D23–D16 D15–D8 D7–D0 BYTE WRITE BYTE WRITE BYTE WRITE BYTE WRITE LONG-WORD OPERAND WRITE TO 8-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-27. Long-Word Operand Write—8-Bit Port 5-36 M68020 USER’S MANUAL MOTOROLA...
  • Page 85: Long-Word Operand Write—16-Bit Port

    D7–D0 WORD WRITE WORD WRITE LONG-WORD WRITE TO 32-BIT PORT LONG-WORD OPERAND WRITE TO 16-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-28. Long-Word Operand Write—16-Bit Port MOTOROLA M68020 USER’S MANUAL 5- 37...
  • Page 86 State 0 MC68020—The write cycle starts in S0. The processor negates ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a write operation, OCS is asserted simultaneously. During S0, the processor places a valid address on A31–A0 and valid function codes on FC2–FC0.
  • Page 87: Read-Modify-Write Cycle

    5.3.3 Read-Modify-Write Cycle The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68020/EC020, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68020/EC020 asserts RMC to indicate that an indivisible operation is occurring.
  • Page 88: Read-Modify-Write Cycle Flowchart

    TERMINATE CYCLE D ; ELSE GO TO E 1) NEGATE DSACK1/DSACK0 UNLOCK BUS 1) NEGATE RMC START NEXT CYCLE This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-29. Read-Modify-Write Cycle Flowchart 5-40 M68020 USER’S MANUAL MOTOROLA...
  • Page 89: Byte Read-Modify-Write Cycle—32-Bit Port (Tas Instruction)

    SIZ0 DSACK1 DSACK0 DBEN D31–D24 D23–D16 D15–8 D7–D0 BERR HALT INDIVISIBLE CYCLE NEXT CYCLE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-30. Byte Read-Modify-Write Cycle—32-Bit Port (TAS Instruction) MOTOROLA M68020 USER’S MANUAL 5- 41...
  • Page 90 State 0 MC68020—The processor asserts ECS and OCS in S0 to indicate the beginning of an external operand cycle. The processor also asserts RMC in S0 to identify a read- modify-write cycle. The processor places a valid address on A31–A0 and valid function codes on FC2–FC0.
  • Page 91 State 5 MC68020—The processor negates AS, DS, and DBEN during S5. If more than one read cycle is required to read in the operand(s), S0–S5 are repeated for each read cycle. When the read cycle(s) are complete, the processor holds the address, R/W , and FC2–FC0 valid in preparation for the write portion of the cycle.
  • Page 92: Cpu Space Cycles

    The CPU space type is encoded on A19–A16 during a CPU space operation and indicates the function that the processor is performing. On the MC68020/EC020, four of the encodings are implemented as shown in Figure 5-31. All unused values are reserved by Motorola for future use.
  • Page 93: Interrupt Acknowledge Bus Cycles

    Refer to Section 6 Exception Processing for details on the recognition of interrupts. The MC68020/EC020 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing.
  • Page 94: Interrupt Acknowledge Cycle Flowchart

    IPL1, and IPL0, respectively). 3. The CPU space type field (A19–A16) is set to 1111, the interrupt acknowledge code. 4. Other address signals (A31–A20, A15–A4, and A0 for the MC68020; A23–A20, A15–A4, and A0 for the MC68EC020) are set to one.
  • Page 95: Interrupt Acknowledge Cycle Timing

    VECTOR # FROM 16-BIT PORT D7–D0 VECTOR # FROM 32-BIT PORT IPL2–IPL0 IPEND INTERRUPT READ CYCLE WRITE STACK ACKNOWLEDGE For the MC68EC020, A23–A4. This signal does not apply to the MC68EC020. Figure 5-33. Interrupt Acknowledge Cycle Timing MOTOROLA M68020 USER’S MANUAL 5- 47...
  • Page 96: Autovector Interrupt Acknowledge Cycle

    When AVEC is asserted instead of DSACK1/DSACK0 during an interrupt acknowledge cycle, the MC68020/EC020 ignores the state of the data bus and internally generates the vector number, the sum of the interrupt level plus 24 ($18). Seven distinct autovectors, which correspond to the seven levels of interrupt available with IPL2–...
  • Page 97: Autovector Operation Timing

    INTERRUPT LEVEL FC2–FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31–D0 IPL2–IPL0 AVEC INTERRUPT WRITE STACK READ CYCLE ACKNOWLEDGE AUTOVECTORED For the MC68EC020, A23–A4. This signal does not apply to the MC68EC020. Figure 5-34. Autovector Operation Timing MOTOROLA M68020 USER’S MANUAL 5- 49...
  • Page 98: Breakpoint Acknowledge Cycle

    1) NEGATE AS AND DS 2) GO TO B 1) PLACE LATCHED DATA IN INSTRUCTION SLAVE NEGATES DSACK1/DSACK0 OR BERR PIPELINE 2) CONTINUE PROCESSING 1) INITIATE ILLEGAL INSTRUCTION PROCESSING Figure 5-35. Breakpoint Acknowledge Cycle Flowchart 5-50 M68020 USER’S MANUAL MOTOROLA...
  • Page 99: Breakpoint Acknowledge Cycle Timing

    BREAKPOINT ENCODING A15–A2 BREAKPOINT NUMBER A1–A0 FC2–FC0 WORD SIZ1 SIZ0 DSACK1 DSACK0 DBEN D23–D16 D15–D8 D7–D0 BERR HALT FETCHED BREAKPOINT READ CYCLE INSTRUCTION ACKNOWLEDGE EXECUTION INSTRUCTION WORD FETCH Figure 5-36. Breakpoint Acknowledge Cycle Timing MOTOROLA M68020 USER’S MANUAL 5- 51...
  • Page 100: Breakpoint Acknowledge Cycle Timing (Exception Signaled)

    SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 BERR HALT INTERNAL READ WITH BERR ASSERTED STACK WRITE PROCESSING For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-37. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 5-52 M68020 USER’S MANUAL MOTOROLA...
  • Page 101: Coprocessor Communication Cycles

    (CpID), and A5–A0 specify the coprocessor interface register to be accessed. The memory management unit of an MC68020/EC020 system is always identified by a CpID of zero and has an extended register select field (A7–A0) in CPU space 0001 for use by the CALLM and RTM access level checking mechanism.
  • Page 102 (e.g., S2, S4, etc.) A—Signal is asserted in this bus state N—Signal is not asserted and/or remains negated in this bus state X—Don’t care S—Signal was asserted in previous state and remains asserted in this state 5-54 M68020 USER’S MANUAL MOTOROLA...
  • Page 103: Bus Errors

    When BERR is issued to terminate a bus cycle, the MC68020/EC020 may enter exception processing immediately following the bus cycle, or it may defer processing the exception.
  • Page 104: Retry Operation

    The processor terminates the bus cycle, negates the control signals (AS, DS, R/W, SIZ1, SIZ0, RMC, and, for the MC68020 only, ECS and OCS), and does not begin another bus cycle until the BERR and HALT signals have been negated by external logic. After a synchronization delay, the processor retries the previous cycle using the same access information (address, function code, size, etc.) The BERR signal should be negated before...
  • Page 105 DBEN D31–D24 D23–D16 D15–D8 D7–D0 BERR HALT BREAKPOINT EXCEPTION ACKNOWLEDGE READ CYCLE STACKING BUS ERROR FETCH For the MC68EC020, A23–A20. This signal does not apply to the MC68EC020. DSACK1/DSACK0 Figure 5-38. Bus Error without MOTOROLA M68020 USER’S MANUAL 5- 57...
  • Page 106 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 IPL2–IPL0 BERR HALT INTERNAL WRITE WITH BERR ASSERTED STACK WRITE PROCESSING For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. DSACK1/DSACK0 Figure 5-39. Late Bus Error with 5-58 M68020 USER’S MANUAL MOTOROLA...
  • Page 107: Late Retry

    FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DATA BUS NOT DRIVEN D31–D0 BERR HALT WRITE CYCLE RETRY SIGNALED HALT RETRY CYCLE For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-40. Late Retry MOTOROLA M68020 USER’S MANUAL 5- 59...
  • Page 108: Halt Operation

    (A31–A0, FC2–FC0, SIZ1, SIZ0, R/W, AS, DS, and, for the MC68020 only, ECS and OCS) are also placed in the high-impedance state. Once bus mastership is returned to the MC68020/EC020, if HALT is still asserted, A31–A0 for the MC68020 or A23–A0 for the MC68EC020, FC2–FC0, SIZ1, SIZ0, and R/W are again...
  • Page 109: Halt Operation Timing

    DSACK1 DSACK0 DBEN D31–D0 BERR HALT HALT READ READ (BUS ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-41. Halt Operation Timing MOTOROLA M68020 USER’S MANUAL 5- 61...
  • Page 110: Bus Synchronization

    NOP instruction for this purpose is not required by most systems. 5.7 BUS ARBITRATION The bus design of the MC68020/EC020 provides for a single bus master at any one time: either the processor or an external device. One or more of the external devices on the bus can have the capability of becoming bus master.
  • Page 111: Mc68020 Bus Arbitration

    • BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. Figure 5-42 is a flowchart of MC68020 bus arbitration for a single device. Figure 5-43 is a timing diagram for the same operation. This technique allows processing of bus requests during data transfer cycles.
  • Page 112: Mc68020 Bus Arbitration Flowchart For Single Request

    PROCESSOR OPERATION 1) NEGATE BGACK Figure 5-42. MC68020 Bus Arbitration Flowchart for Single Request The timing diagram (see Figure 5-43) shows that BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the processor and one device capable of bus mastership.
  • Page 113: Mc68020 Bus Arbitration Operation Timing For Single Request

    A31–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 BGACK PROCESSOR DMA DEVICE PROCESSOR Figure 5-43. MC68020 Bus Arbitration Operation Timing for Single Request MOTOROLA M68020 USER’S MANUAL 5- 65...
  • Page 114: Bus Request (Mc68020)

    5.7.1.2 BUS GRANT (MC68020). The processor asserts BG as soon as possible after receipt of the bus request. BG assertion immediately follows internal synchronization except during a read-modify-write cycle or follows an internal decision to execute a bus cycle.
  • Page 115: Bus Arbitration Control (Mc68020)

    5.7.1.4 BUS ARBITRATION CONTROL (MC68020). The bus arbitration control unit in the MC68020 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68020 are internally synchronized in a maximum of two cycles of the processor clock.
  • Page 116 R and A. The MC68020 does not allow arbitration of the external bus during the read-modify-write sequence. For the duration of this sequence, the MC68020 ignores the BR input. If mastership of the MC68020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence.
  • Page 117: Mc68020 Bus Arbitration Operation Timing—Bus Inactive

    A31–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 BGACK BUS INACTIVE (ARBITRATION PERMITTED ALTERNATE MASTER PROCESSOR PROCESSOR WHILE THE PROCESSOR IS INACTIVE OR HALTED) Figure 5-45. MC68020 Bus Arbitration Operation Timing—Bus Inactive MOTOROLA M68020 USER’S MANUAL 5- 69...
  • Page 118: Mc68Ec020 Bus Arbitration

    B R; it is usually asserted as soon as BR has been synchronized and recognized, except when the MC68020 has made an internal decision to execute a bus cycle. Then, the assertion of BG is deferred until the bus cycle has begun. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal.
  • Page 119: Bus Request (Mc68Ec020)

    BG is deferred until the bus cycle has begun. BG may be routed through a daisy-chained network or through a specific priority-encoded network. The processor allows any type of external arbitration that follows the protocol. MOTOROLA M68020 USER’S MANUAL 5- 71...
  • Page 120: Mc68Ec020 Bus Arbitration Operation Timing For Single Request

    A23–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 D31–D0 PROCESSOR DMA DEVICE PROCESSOR Figure 5-47. MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 M68020 USER’S MANUAL MOTOROLA...
  • Page 121: Bus Arbitration Control (Mc68Ec020)

    STATE 0 STATE 4 STATE1 STATE 3 STATE 2 STATE 5 STATE 6 R—BUS REQUEST G—BUS GRANT T —THREE-STATE CONTROL TO BUS CONTROL LOGIC X—DON'T CARE Figure 5-48. MC68EC020 Bus Arbitration State Diagram MOTOROLA M68020 USER’S MANUAL 5- 73...
  • Page 122 If mastership of the MC68EC020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 5-49. 5-74 M68020 USER’S MANUAL MOTOROLA...
  • Page 123: Mc68Ec020 Bus Arbitration Operation Timing—Bus Inactive

    BGACK and the negation of BR by the alternate bus master. Figure 5-50 assumes the alternate bus master does not assume bus mastership until the MC68EC020 AS is negated and MC68EC020 BG is asserted. MOTOROLA M68020 USER’S MANUAL 5- 75...
  • Page 124: Reset Operation

    RESET should be asserted for at least 520 clock periods to ensure that the processor resets. Asserting RESET for 10 clock periods is sufficient for resetting the processor logic; the additional clock periods prevent a RESET instruction from overlapping the external RESET signal. 5-76 M68020 USER’S MANUAL MOTOROLA...
  • Page 125: Initial Reset Operation Timing

    RESET instruction must extend beyond the reset period of the instruction by at least eight clock cycles to reset the processor. Figure 5-52 shows the timing information for the RESET instruction. MOTOROLA M68020 USER’S MANUAL 5- 77...
  • Page 126: Reset Instruction Timing

    A31–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 HALT RESET RESET INTERNAL RESUME NORMAL READ 512 CLOCKS OPERATION For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-52. RESET Instruction Timing 5-78 M68020 USER’S MANUAL MOTOROLA...
  • Page 127: Exception Processing

    An introduction to exception processing, as one of the processing states of the MC68020/EC020, is given in Section 2 Processing States. This section describes exception processing in detail, describing the processing for each type of exception.
  • Page 128 6-1 contains a description of all the exception vector offsets defined for the MC68020/EC020. As shown in Table 6-1, the first 64 vectors are defined by Motorola, and 192 vectors are reserved for interrupt vectors defined by the user. However, external devices may use vectors reserved for internal purposes at the discretion of the system designer.
  • Page 129: Exception Vector Assignments

    FPCP Underflow FPCP Operand Error FPCP Overflow FPCP Signaling NAN Unassigned, Reserved PMMU Configuration PMMU Illegal Operation PMMU Access Level Violation 59–63 Unassigned, Reserved 64–255 User-Defined Vectors (192) SP—Supervisor Program Space SD—Supervisor Data Space MOTOROLA M68020 USER’S MANUAL 6- 3...
  • Page 130: Reset Exception

    HALT signal to indicate the halted condition. Execution of the RESET instruction does not cause a reset exception, nor does it affect any internal registers, but it does cause the MC68020/EC020 to assert the RESET signal, resetting all external devices.
  • Page 131: Reset Operation Flowchart

    SR on the active supervisor stack. The saved PC value is the logical address of the instruction that was executing at the time the fault was detected. This is not necessarily the instruction that initiated the bus cycle since the processor overlaps MOTOROLA M68020 USER’S MANUAL 6- 5...
  • Page 132: Address Error Exception

    The information saved on the stack is sufficient to identify the cause of the bus fault and recover from the error. For efficiency, the MC68020/EC020 uses two different bus error stack frame formats. When the bus error exception is taken at an instruction boundary, less information is required to recover from the error, and the processor builds the short bus fault stack frame as shown in Table 6-5.
  • Page 133: Illegal Instruction And Unimplemented Instruction Exceptions

    An illegal instruction is an instruction that contains any bit pattern in its first word that does not correspond to the bit pattern of the first word of a valid MC68020/EC020 instruction or a MOVEC instruction with an undefined register specification field in the first extension word.
  • Page 134: Privilege Violation Exception

    The saved value of the PC is the logical address of the first word of the instruction that caused the privilege violation. Instruction execution resumes after the required prefetches from the address in the privilege violation exception vector. M68020 USER’S MANUAL MOTOROLA...
  • Page 135: Trace Exception

    6.1.7 Trace Exception To aid in program development, the M68000 processors include an instruction-by- instruction tracing capability. The MC68020/EC020 can be programmed to trace all instructions or only instructions that change program flow. In the trace mode, an instruction generates a trace exception after it completes execution, allowing a debugger program to monitor execution of a program.
  • Page 136: Format Error Exception

    The cpRESTORE instruction passes the format word of the coprocessor state frame to the coprocessor for validation. If the coprocessor does not recognize the format value, it signals the MC68020/EC020 to take a format error exception. Refer to Section 7 Coprocessor Interface Description for details of coprocessor-related exceptions.
  • Page 137: Interrupt Exceptions

    6.1.9 Interrupt Exceptions When a peripheral device requires the services of the MC68020/EC020 or is ready to send information that the processor requires, it may signal the processor to take an interrupt exception. The interrupt exception transfers control to a routine that responds appropriately.
  • Page 138: Interrupt Pending Procedure

    6 and one for level 7. When the MC68020/EC020 processes a level 6 interrupt, the interrupt priority mask is automatically updated with a value of 6 before entering the handler routine so that subsequent level 6 interrupts are masked.
  • Page 139 3 and then raised back to level 6, and a second MOTOROLA M68020 USER’S MANUAL 6- 13...
  • Page 140: Interrupt Recognition Examples

    6 interrupt is not processed. However, if the MC68020/EC020 is handling a level 7 interrupt (I2–I0 in the SR set to 111) and the external request is lowered to level 3 and then raised back to level 7, a second level 7 interrupt is processed. The second level 7 interrupt is processed because the level 7 interrupt is transition sensitive.
  • Page 141: Assertion Of Ipend (Mc68020 Only)

    The MC68020 asserts IPEND (note that IPEND is not implemented in the MC68EC020) when it makes an interrupt request pending. Figure 6-4 shows the assertion of IPEND relative to the assertion of an interrupt level on IPL2 – IPL0 . IPEND signals to external devices that an interrupt exception will be taken at an upcoming instruction boundary (following any higher priority exception).
  • Page 142: Interrupt Exception Processing Flowchart

    PREFETCH 3 WORDS BEGIN EXECUTION OF THE INTERRUPT END OF EXCEPTION PROCESSING HANDLER ROUTINE OR PROCESS A FOR THE INTERRUPT HIGHER PRIORITY EXCEPTION Does not apply to the MC68EC020. Figure 6-5. Interrupt Exception Processing Flowchart 6-16 M68020 USER’S MANUAL MOTOROLA...
  • Page 143 For the MC68020, if no higher priority interrupt has been synchronized, the IPEND signal is negated during state 0 (S0) of an interrupt acknowledge cycle, and the IPL2–IPL0 signals for the interrupt being acknowledged can be negated at this time. For the MC68EC020, if no higher priority interrupt has been synchronized, the IPL2–IPL0 signals...
  • Page 144: Breakpoint Instruction Exception

    6.1.10 Breakpoint Instruction Exception To use the MC68020/EC020 in a hardware emulator, it must provide a means of inserting breakpoints in the emulator code and of performing appropriate operations at each breakpoint. For the MC68000 and MC68008, this can be done by inserting an illegal instruction at the breakpoint and detecting the illegal instruction exception from its vector location.
  • Page 145: Breakpoint Instruction Flowchart

    Exception processing begins before instruction is Line F, Privilege Violation, cp Preinstruction executed. 4.0—cp Postinstruction Exception processing begins when current instruction 4.1—Trace or previous exception processing has completed. 4.2—Interrupt NOTE: 0.0 is the highest priority; 4.2 is the lowest. MOTOROLA M68020 USER’S MANUAL 6- 19...
  • Page 146: Return From Exception

    6.1.12 Return from Exception After the MC68020/EC020 has completed exception processing for all pending exceptions, it resumes normal instruction execution at the address in the vector for the last exception processed. Once the exception handler has completed execution, the processor must return to the system context prior to the exception (if possible).
  • Page 147: Rte Instruction For Throwaway Four-Word Frame

    Otherwise, the processor reads the entire frame into the proper internal registers, deallocates the stack, and resumes normal processing. Once the processor begins to load the frame to restore its internal state, the assertion of the BERR signal MOTOROLA M68020 USER’S MANUAL 6- 21...
  • Page 148: Bus Fault Recovery

    SSW applies to data cycles only. Data and instruction stream faults may be pending simultaneously; the fault handler should be able to recognize any combination of the FC, FB, RC, RB, and DF bits. 6-22 M68020 USER’S MANUAL MOTOROLA...
  • Page 149: Special Status Word Format

    B. The address space for the bus cycle is the program space for the privilege level indicated in the copy of the SR on the stack. If the RB bit is clear, the words on the MOTOROLA M68020 USER’S MANUAL...
  • Page 150: Using Software To Complete The Bus Cycles

    1 = Rerun faulted bus cycle or run pending prefetch 0 = Do not rerun bus cycle Bits 11–9—Reserved by Motorola DF—Fault/Rerun Flag If the DF bit is set, a data fault has occurred and caused the exception. If the DF bit is set when the processor reads the stack frame, it reruns the faulted data access;...
  • Page 151: Completing The Bus Cycles With Rte

    The fault occurs again unless the cause of the fault, such as a nonresident page in a virtual memory system, has been corrected. If the RB or RC bit is set and the MOTOROLA M68020 USER’S MANUAL 6- 25...
  • Page 152: Coprocessor Considerations

    When the MC68020/EC020 writes or reads a stack frame, it uses long-word operand transfers wherever possible. Using a long-word-aligned stack pointer with memory that is on a 32-bit port greatly enhances exception processing performance.
  • Page 153 During Coprocessor +$08 INSTRUCTION ADDRESS that caused the exception Instruction +$0C (supported with 'null INTERNAL REGISTERS, come again with 4 WORDS +$12 interrupts allowed' primitive) COPROCESSOR MIDINSTRUCTION STACK FRAME (10 WORDS) — FORMAT $9 MOTOROLA M68020 USER’S MANUAL 6- 27...
  • Page 154 INTERNAL REGISTERS, 2 WORDS +$2A +$2C DATA INPUT BUFFER +$30 INTERNAL REGISTERS, 3 WORDS +$36 +$38 VERSION # INTERNAL INFORMATION INTERNAL REGISTERS, 18 WORDS +$5A LONG BUS FAULT STACK FRAME (46 WORDS) — FORMAT $B 6-28 M68020 USER’S MANUAL MOTOROLA...
  • Page 155: Coprocessor Interface Description

    This section is intended for designers who are implementing coprocessors to interface with the MC68020/EC020. The designer of a system that uses one or more Motorola coprocessors (the MC68881 or MC68882 floating-point coprocessor, for example) does not require a detailed knowledge of the M68000 coprocessor interface.
  • Page 156: Interface Features

    The communication protocol defined for the M68000 coprocessor interface is described in 7.2 Coprocessor Instruction Types. The algorithms that implement the M68000 coprocessor interface are provided in the microcode of the MC68020/EC020 and are completely transparent to the MC68020/EC020 programming model. For example, floating-point operations are not implemented in the MC68020/EC020 hardware.
  • Page 157: Coprocessor Instruction Format

    (CpID) field. The MC68020/EC020 uses the CpID field to indicate the coprocessor to which the instruction applies. F-line operation words, in which the CpID is zero, are not coprocessor instructions for the MC68020/EC020. Instructions with a CpID of zero and a nonzero type field are unimplemented instructions that cause the MOTOROLA M68020 USER’S MANUAL...
  • Page 158: Coprocessor System Interface

    CpID equal to zero (except via the MOVES instruction). CpID codes of 000–101 are reserved for current and future Motorola coprocessors, and CpID codes of 110–111 are reserved for user-defined coprocessors. The Motorola CpID code of 001 designates the MC68881 or MC68882 floating-point coprocessor.
  • Page 159: Processor-Coprocessor Interface

    Figure 7-2. Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage The MC68020/EC020 accesses the registers in the CIR set using standard asynchronous bus cycles. Thus, the bus interface implemented by a coprocessor for its interface register set must satisfy the MC68020/EC020 address, data, and control signal timing. The MC68020/EC020 bus operation is described in detail in Section 5 Bus Operation.
  • Page 160 The FC2–FC0 and A19–A16 signals indicate a coprocessor access; A15–A13 indicate which of the possible eight coprocessors (000–111) is being accessed. Bits A31–A20 and A12–A5 of the MC68020 address bus and bits A23–A20 and A12–A5 of the MC68EC020 address bus are always zero during a coprocessor access.
  • Page 161: Coprocessor Instruction Types

    The category name indicates the type of operations provided by the coprocessor instructions in the category. The instruction category also determines the CIR accessed by the MC68020/EC020 to initiate instruction and communication protocols between the main processor and the coprocessor necessary for instruction execution.
  • Page 162: Coprocessor General Instructions

    Programmer’s Reference Manual ). During the execution of a cpGEN instruction, the coprocessor can use a coprocessor response primitive to request that the MC68020/EC020 perform an effective address calculation necessary for that instruction. Using the effective address specifier field of the F-line operation code, the processor then determines the effective addressing mode.
  • Page 163 The main processor can then execute the next instruction in the instruction stream. However, if a trace exception is pending, the MC68020/EC020 does not terminate communication with the coprocessor until the coprocessor indicates that it has completed all processing associated with the cpGEN instruction (refer to 7.5.2.5 Trace Exceptions).
  • Page 164 NOTES: 1. "Come Again" indicates that further service of the main processor is being requested by the coprocessor. 2. The next instruction should be the operation word pointed to by the ScanPC at this point. The operation of the MC68020/EC020 ScanPC is discussed in 7.4.1 ScanPC.
  • Page 165 "Come Again" when used during the execution of a conditional category instruction. If a "Come Again" attribute is not indicated in one of these primitives, the main processor will initiate protocol violation exception processing (see 7.5.2.1 Protocol Violations). Figure 7-8. Coprocessor Interface Protocol for Conditional Category Instructions MOTOROLA M68020 USER’S MANUAL 7- 11...
  • Page 166: Branch On Coprocessor Condition Instruction

    Bits 5–0 of the F-line operation word contain the coprocessor condition selector field. The MC68020/EC020 writes the entire operation word to the condition CIR to initiate execution of the branch instruction by the coprocessor.
  • Page 167 CIR to determine its next action. The coprocessor can MOTOROLA M68020 USER’S MANUAL 7- 13...
  • Page 168: Set On Coprocessor Condition Instruction

    The second word of the cpScc instruction format contains the coprocessor condition selector field in bits 5–0. Bits 15–6 of this word are reserved by Motorola and should be zero to ensure compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpScc instruction.
  • Page 169 The second word of the cpDBcc instruction format contains the coprocessor condition selector field in bits 5–0 and should contain zeros in bits 15–6 (reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpDBcc instruction.
  • Page 170: Format

    (–1) after being decremented, the main processor branches to the destination address to continue instruction execution. The MC68020/EC020 adds the displacement to the scanPC (refer to 7.4.1 ScanPC) to determine the address of the next instruction. The scanPC must point to the 16-bit displacement in the instruction stream when the destination address is calculated.
  • Page 171: Protocol

    The second word of the cpTRAPcc instruction format contains the coprocessor condition selector in bits 5–0 and should contain zeros in bits 15–6 (these bits are reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpTRAPcc instruction.
  • Page 172: Coprocessor Internal State Frames

    Figure 7-14 shows the format of a coprocessor state frame. The format and length fields of the coprocessor state frame format comprise the format word. During execution of the cpSAVE instruction, the MC68020/EC020 calculates the state frame effective address from information in the operation word of the instruction and stores a format word at this effective address.
  • Page 173: Empty/Reset Format Word

    The MC68020/EC020 interprets the reserved format codes ($03–$0F) as invalid format words. The lower byte of the coprocessor format word specifies the size in bytes (which must be a multiple of four) of the coprocessor state frame.
  • Page 174: Not-Ready Format Word

    In this situation, the coprocessor can return the invalid format word when the main processor reads the save CIR to initiate the cpSAVE instruction while either another cpSAVE or cpRESTORE instruction is executing. If the 7-20 M68020 USER’S MANUAL MOTOROLA...
  • Page 175: Valid Format Word

    Figure 7-15. Coprocessor Context Save Instruction Format (cpSAVE) The control alterable and predecrement addressing modes are valid for the cpSAVE instruction. Other addressing modes cause the MC68020/EC020 to initiate F-line emulator exception processing as described in 7.5.2.2 F-Line Emulator Exceptions.
  • Page 176 MC68020/EC020 initiates format error exception processing (refer to 7.5.1.5 Format Errors). The coprocessor and main processor coordinate the transfer of the internal state of the coprocessor using the operand CIR. The MC68020/EC020 completes the coprocessor context save by repeatedly reading the operand CIR and writing the 7-22 M68020 USER’S MANUAL...
  • Page 177: Coprocessor Context Restore Instruction

    Following a cpSAVE instruction, the coprocessor should be in an idle state—that is, not executing any coprocessor instructions. The cpSAVE instruction is a privileged instruction. When the MC68020/EC020 identifies a cpSAVE instruction, it checks the S-bit in the SR to determine whether it is operating at the supervisor privilege level.
  • Page 178 PROCEED WITH EXECUTION OF NEXT INSTRUCTION NOTES: 1. See 7.6.1.5 Format Error. 2. The MC68020/EC020 uses the length field in the format word read during M2 to determine the number of bytes to read from memory and write to the operand CIR.
  • Page 179: Coprocessor Interface Register Set

    (refer to 7.5.1.5 Format Errors). The cpRESTORE instruction is a privileged instruction. When the MC68020/EC020 accesses a cpRESTORE instruction, it checks the S-bit in the SR. If the MC68020/EC020 attempts to execute a cpRESTORE instruction while at the user privilege level (S-bit in the SR is clear), it initiates privilege violation exception processing without accessing any of the CIRs (refer to 7.5.2.3 Privilege Violations).
  • Page 180: Save Cir

    (XA) in the control CIR. The MC68020/EC020 sets the abort bit (AB) in the control CIR to abort any coprocessor instruction in progress. (The 14 most significant bits of both masks are undefined.) The MC68020/EC020 aborts a coprocessor instruction when it...
  • Page 181: Condition Cir

    5–0 of the 16-bit condition CIR. Bits 15–6 are undefined and reserved by Motorola. The offset from the base address of the CIR set for the condition CIR is $0E. Figure 7-20 shows the format of the condition CIR.
  • Page 182: Register Select Cir

    General Format, consist of detailed descriptions of the M68000 coprocessor response primitives supported by the MC68020/EC020. Any response primitive that the MC68020/EC020 does not recognize causes it to initiate protocol violation exception processing (refer to 7.5.2.1 Protocol Violations). This processing of undefined primitives supports emulation of extensions to the M68000 coprocessor response primitive set by the protocol violation exception handler.
  • Page 183: Scanpc

    During the execution of conditional category instructions, when the coprocessor terminates the instruction protocol, the MC68020/EC020 assumes that the scanPC is pointing to the word following the last of any coprocessor-defined extension words in the instruction format.
  • Page 184 (main processor read). If the operation indicated by a given response primitive does not involve an explicit operand transfer, the value of this bit depends on the particular primitive encoding. 7-30 M68020 USER’S MANUAL MOTOROLA...
  • Page 185: Busy Primitive

    The MC68020/EC020 responds to the busy primitive differently in a special case that can occur during a breakpoint operation (refer to Section 6 Exception Processing). This...
  • Page 186: Null Primitive

    The TF bit is only relevant for null primitives with CA = 0 that are used by the coprocessor during the execution of a conditional instruction. The MC68020/EC020 processes a null primitive with CA = 1 in the same manner whether executing a general or conditional category coprocessor instruction. If the coprocessor sets CA and IA in the null primitive, the main processor services pending interrupts using a midinstruction stack frame (refer to Figure 7-43) and reads the response CIR again.
  • Page 187: Null Coprocessor Response Primitive Encodings

    Coprocessor Instruction Completed; Main Processor Completes Instruction Service Pending Exceptions or Execute Execution Based on TF = c. Next Instruction x = Don't Care c = 1 or 0 Depending on Coprocessor Condition Evaluation MOTOROLA M68020 USER’S MANUAL 7- 33...
  • Page 188: Supervisor Check Primitive

    When the MC68020/EC020 reads the supervisor check primitive from the response CIR, it checks the value of the S-bit in the SR. If S = 0 (main processor operating at user privilege level), the main processor aborts the coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR).
  • Page 189: Transfer From Instruction Stream Primitive

    CIR. If the length field is not an even multiple of four bytes, the last two bytes from the instruction stream are transferred using a word write to the operand CIR. MOTOROLA M68020 USER’S MANUAL 7- 35...
  • Page 190: Evaluate And Transfer Effective Address Primitive

    After the effective address is calculated, the resulting 32-bit value is written to the operand address CIR. The MC68020/EC020 only calculates effective addresses for control alterable addressing modes in response to this primitive. If the addressing mode in the operation word is not a control alterable mode, the main processor aborts the instruction by writing a $0001 to the control CIR and initiates F-line emulation exception processing (refer to 7.5.2.2 F-Line...
  • Page 191: Valid Effective Address Field Codes

    Any Effective Address (No Restriction) Even when the valid EA fields specified in the primitive and in the instruction operation word match, the MC68020/EC020 initiates protocol violation exception processing if the primitive requests a write to an unalterable effective address.
  • Page 192: Write To Previously Evaluated Effective Address Primitive

    The MC68020/EC020 sign-extends a byte or word-sized operand to a long-word value when it is transferred to an address register (A7–A0) using this primitive with the register direct effective addressing mode.
  • Page 193 For example, if the previously evaluated effective address was PC relative and the MC68020/EC020 is at the user privilege level (S = 0 in SR), the MC68020/EC020 writes to user data space at the previously calculated program relative address (the 32-bit value in the temporary internal register of the processor).
  • Page 194: Take Address And Transfer Data Primitive

    Transfer Data Primitive does not replace the effective address value that has been calculated by the MC68020/EC020. The address that the main processor obtains in response to the take address and transfer data primitive is not available to the write to previously evaluated effective address primitive.
  • Page 195: Transfer To/From Top Of Stack Primitive

    The transfer single main processor register primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. MOTOROLA M68020 USER’S MANUAL 7- 41...
  • Page 196: Transfer Main Processor Control Register Primitive

    CIR. This code determines which main processor control register is transferred. Table 7-5 lists the valid control register select codes. If the control register select code is not valid, the MC68020/EC020 initiates protocol violation exception processing (refer to 7.5.2.1 Protocol Violations).
  • Page 197: Transfer Multiple Main Processor Registers Primitive

    This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-37 shows the format of the transfer multiple coprocessor registers primitive. MOTOROLA M68020 USER’S MANUAL 7- 43...
  • Page 198: Transfer Multiple Coprocessor Registers Primitive Format

    (DR = 1), the control alterable and predecrement addressing modes are valid. Invalid addressing modes cause the MC68020/EC020 to abort the instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR) and to initiate F-line emulator exception processing (refer to 7.5.2.2 F-Line Emulator Exceptions).
  • Page 199: Transfer Status Register And Scanpc Primitive

    7.4.17 Transfer Status Register and ScanPC Primitive The transfer status register and the scanPC primitive transfers values between the coprocessor and the MC68020/EC020 SR. On an optional basis, the scanPC also makes transfers. This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing.
  • Page 200: Take Preinstruction Exception Primitive

    S-bit of the SR. If the MC68020/EC020 is operating in the trace on change of flow mode (T1, T0 in the SR = 01) when the coprocessor instruction begins to execute and if this primitive is issued with DR = 1 (from coprocessor to main processor), the MC68020/EC020 prepares to take a trace exception.
  • Page 201: Mc68020/Ec020 Preinstruction Stack Frame

    Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the four-word stack frame format shown in Figure 7-41. STATUS REGISTER PROGRAM COUNTER VECTOR NUMBER Figure 7-41.
  • Page 202: Take Midinstruction Exception Primitive

    CIR. The MC68020/EC020 then performs exception processing as described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the 10-word stack frame format shown in Figure 7-43.
  • Page 203: Take Postinstruction Exception Primitive

    7.3.2 Control CIR). The MC68020/EC020 then performs exception processing as described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the six- word stack frame format shown in Figure 7-45.
  • Page 204: Coprocessor-Detected Exceptions

    When the MC68020/EC020 receives the take postinstruction exception primitive, it assumes that the coprocessor either completed or aborted the instruction with an exception. If the exception handler does not modify the stack frame, the MC68020/EC020 returns from the exception handler to begin execution at the location specified by the scanPC field of the stack frame.
  • Page 205: Coprocessor-Detected Protocol Violations

    7.4.19 Take Midinstruction Exception Primitive. If the exception handler does not modify the stack frame, the MC68020/EC020 returns from the exception handler and reads the response CIR. MOTOROLA M68020 USER’S MANUAL...
  • Page 206: Coprocessor-Detected Illegal Command Or Condition Words

    7.4.18 Take Preinstruction Exception Primitive. If the exception handler does not modify the main processor stack frame, an RTE instruction causes the MC68020/EC020 to reinitiate the instruction that took the exception. The coprocessor designer should ensure that the state of the coprocessor is not irrecoverably altered by an illegal command or condition exception if the system supports emulation of the unrecognized command or condition word.
  • Page 207: Format Errors

    14. Thus, if the exception handler does not modify the stack frame, the MC68020/EC020 restarts the cpRESTORE instruction when the RTE instruction in the handler is executed. If the coprocessor returns the invalid format code when the main processor reads the save CIR to initiate a cpSAVE instruction, the main processor performs format error exception processing as outlined for the cpRESTORE instruction.
  • Page 208: Exceptions Related To Primitive Processing

    Transfer Status and ScanPC Protocol: If Used with Conditional Instruction Other: 1. Trace—Trace Made Pending if MC68020/EC020 in “Trace on Change of Flow” Mode and DR = 1 2. Address Error—If Odd Value Written to ScanPC Take Preinstruction, Midinstruction, or Postinstruction Exception Exception Depends on Vector Supplies in Primitive Use of this primitive with CA = 0 will cause protocol violation on conditional instructions.
  • Page 209: F-Line Emulator Exceptions

    If the main processor determines that an F-line operation word is not valid, it initiates F-line emulator exception processing. Any F-line operation word with bits 8–6 = 110 or 111 causes the MC68020/EC020 to initiate exception processing without initiating any communication with the coprocessor for that instruction.
  • Page 210: Privilege Violations

    MC68020/EC020 takes a trace exception after completing each instruction. In the trace on change of flow mode, the MC68020/EC020 takes a trace exception after each instruction that alters the SR or places an address other than the address of the next instruction in the PC.
  • Page 211: Interrupts

    If T1, T0 = 01 in the MC68020/EC020 SR (trace on change of flow mode) when a general category instruction is initiated, a trace exception is taken for the instruction only when the coprocessor issues a transfer status register and scanPC primitive with DR = 1 during the execution of that instruction.
  • Page 212: Format Errors

    If the MC68020/EC020 reads a format word with an invalid length field from the save CIR during the cpSAVE instruction, it aborts the coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR) and...
  • Page 213: Coprocessor Reset

    The system designer can design a coprocessor to be reset and initialized by both reset types or by external reset signals only. To be consistent with the MC68020/EC020 design, the coprocessor should be affected by external reset signals only and not by RESET instructions, because the coprocessor is an extension to the main processor programming model and to the internal state of the MC68020/EC020.
  • Page 214 Busy Transfer Multiple Coprocessor Registers LENGTH Transfer Status Register and ScanPC Supervisor Check Take Address and Transfer Data LENGTH Transfer Multiple Main Processor Registers Transfer Operation Word Null Evaluate and Transfer Effective Address 7-60 M68020 USER’S MANUAL MOTOROLA...
  • Page 215 Transfer from Instruction Stream LENGTH Evaluate Effective Address and Transfer Data VALID EA LENGTH Take Preinstruction Exception VECTOR NUMBER Take Midinstruction Exception VECTOR NUMBER Take Postinstruction Exception VECTOR NUMBER Write to Previously Evaluated Effective Address LENGTH MOTOROLA M68020 USER’S MANUAL 7- 61...
  • Page 216: Instruction Execution Timing

    8.1.1 Instruction Cache and Prefetch The on-chip cache of the MC68020/EC020 is an instruction-only cache. Its purpose is to increase execution efficiency by providing a quick store for instructions. Instruction prefetches that hit in the cache will occur with no delay in instruction execution.
  • Page 217: Operand Misalignment

    (e.g., due to a branch to an odd-word location), the MC68020/EC020 will read the even word associated with the long-word base address at the same time as (32-bit memory) or before (8- or 16-bit memory) the odd word is read.
  • Page 218: Instruction Execution Overlap

    MOVE to SR instruction to lower the interrupt mask level. Otherwise, the MOVE to SR instruction may complete before the write is accomplished, and a new interrupt exception will be generated for an old interrupt request. MOTOROLA M68020 USER’S MANUAL 8- 3...
  • Page 219: Instruction Stream Timing Examples

    + 8 ADD #4 ••• Figure 8-3 shows processor activity on the first example instruction stream. It shows the activity of the external bus, the bus controller, the sequencer, and the attributed instruction execution time. M68020 USER’S MANUAL MOTOROLA...
  • Page 220: Processor Activity For Example 1

    MOVE #3 is absorbed by the execution time of MOVE #3. This overlap shortens the effective execution time of ADD #4 by one clock, giving it an attributed execution time of one clock. MOTOROLA M68020 USER’S MANUAL 8- 5...
  • Page 221: Processor Activity For Example 2

    Although the total execution time of the instruction segment does not change in this example, the individual instruction times are significantly different. This example demonstrates that the effects of overlap are not only instruction-sequence dependent but are also dependent upon the alignment of the instruction stream in memory. M68020 USER’S MANUAL MOTOROLA...
  • Page 222: Processor Activity For Example 3

    Since prefetch occurs with no delay, the bus controller is idle more often. Example 4 Idle clock cycles, such as those shown in example 3, are useful in MC68020/EC020 systems that require wait states when accessing external memory. This fact is illustrated in example 4 (see Figure 8-6) with the following assumptions: 1.
  • Page 223: Processor Activity For Example 4

    13 clocks. Examples 1–4 demonstrate the complexity of instruction timing calculation for the MC68020/EC020. It is impossible to anticipate individual instruction timing as an absolute number of clock cycles due to the dependency of overlap on the instruction sequence and alignment as well as the number of wait states in memory.
  • Page 224: Instruction Timing Tables

    8.2 INSTRUCTION TIMING TABLES The instruction times given in the following illustration include the following assumptions about the MC68020/EC020 system: 1. All operands are long-word aligned as is the stack, 2. The data bus is 32 bits, and 3. Memory access occurs with no wait states (three-cycle read/write).
  • Page 225 1.MULU.L (D7),D1:D2 #<data>.W,Dn MUL.L EA,Dn 2.BFCLR $6000{0:8} #<data>.W.,$XXX.W BFCLR Mem (<5 bytes) 3.DIVS.L #$10000,D3:D4 #<data>.W,#<data>.L DIVS.L EA, Dn Execution time = 2 + 43 + 5 + 16 + 6 + 90 = 102 clock periods 8-10 M68020 USER’S MANUAL MOTOROLA...
  • Page 226: Instruction Timings From Timing Tables

    BC, CC, or WC timing. Table 8-3. Observed Instruction Timings Example 1 Example 2 Example 3 Example 4 Instruction #1) MOVE.L D4,(A1)+ #2) ADD.L D4,D5 #3) MOVE.L (A1),–(A2) #4) ADD.L D5,D6 Total (16) (16) (12) (13) MOTOROLA M68020 USER’S MANUAL 8- 11...
  • Page 227 Although the timing tables cannot accurately predict the instruction timing that would be observed when executing an instruction stream on the MC68020/EC020, the tables can be used to calculate best-case and worst-case bounds for instruction timing. Absolute instruction timing must be measured by using the microprocessor itself to execute the target instruction stream.
  • Page 228: Fetch Effective Address

    B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA M68020 USER’S MANUAL 8- 13...
  • Page 229: Fetch Immediate Effective Address

    #<data >.W,(d 32 ,B) 10(1/0/0) 15(1/0/0) 19(1/3/0) #<data >.L,(d 32 ,B) 11(1/0/0) 17(1/0/0) 21(1/3/0) #<data >.W,([B],I) 9(2/0/0) 14(2/0/0) 16(2/2/0) #<data >.L,([B],I) 10(2/0/0) 16(2/0/0) 18(2/2/0) #<data >.W,([B],I,d 16 ) 11(2/0/0) 16(2/0/0) 19(2/2/0) #<data >.L,([B],I,d 16 ) 12(2/0/0) 18(2/0/0) 21(2/2/0) 8-14 M68020 USER’S MANUAL MOTOROLA...
  • Page 230 B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA M68020 USER’S MANUAL 8- 15...
  • Page 231: Calculate Effective Address

    B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. 8-16 M68020 USER’S MANUAL MOTOROLA...
  • Page 232: Calculate Immediate Effective Address

    #<data >.L,([B],I,d 11(1/0/0) 17(1/0/0) 20(1/2/0) #<data >.W,([B],I,d 10(1/0/0) 15(1/0/0) 19(1/2/0) #<data >.L,([d 16 ,B],I,d 11(1/0/0) 17(1/0/0) 21(1/3/0) #<data >.W,([d ,B],I) 10(1/0/0) 15(1/0/0) 18(1/2/0) #<data >.L,([d ,B],I) 11(1/0/0) 17(1/0/0) 20(1/2/0) #<data >.W,([d ,B],I,d 12(1/0/0) 17(1/0/0) 21(1/2/0) MOTOROLA M68020 USER’S MANUAL 8- 17...
  • Page 233 B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. 8-18 M68020 USER’S MANUAL MOTOROLA...
  • Page 234: Jump Effective Address

    B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA M68020 USER’S MANUAL 8- 19...
  • Page 235: Move Instruction

    13(2/0/0) 13(2/0/0) 16(2/0/1) 16(2/0/1) 16(2/0/1) 16(2/0/1) 16(2/0/1) 18(2/0/1) ,B],I) 15(2/0/0) 15(2/0/0) 18(2/0/1) 18(2/0/1) 18(2/0/1) 18(2/0/1) 18(2/0/1) 20(2/0/1) ,B],I,d 17(2/0/0) 17(2/0/0) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 22(2/0/1) ,B],I,d 17(2/0/0) 17(2/0/0) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 22(2/0/1) 8-20 M68020 USER’S MANUAL MOTOROLA...
  • Page 236 20(2/0/1) 21(2/0/1) 21(2/0/1) 25(2/0/1) 23(3/0/1) 25(3/0/1) 26(3/0/1) ,B],I) 20(2/0/1) 22(2/0/1) 23(2/0/1) 23(2/0/1) 27(2/0/1) 25(3/0/1) 27(3/0/1) 28(3/0/1) ,B],I,d 22(2/0/1) 24(2/0/1) 25(2/0/1) 25(2/0/1) 29(2/0/1) 27(3/0/1) 29(3/0/1) 30(3/0/1) ,B],I,d 22(2/0/1) 24(2/0/1) 25(2/0/1) 25(2/0/1) 29(2/0/1) 27(3/0/1) 29(3/0/1) 30(3/0/1) MOTOROLA M68020 USER’S MANUAL 8- 21...
  • Page 237 ,B],I,d 25(3/0/1) 27(3/0/1) 28(3/0/1) 29(3/0/1) 31(3/0/1) 32(3/0/1) ,B],I,d 25(3/0/1) 27(3/0/1) 28(3/0/1) 29(3/0/1) 31(3/0/1) 32(0/0/1) ,B],I) 27(3/0/1) 29(3/0/1) 30(3/0/1) 31(3/0/1) 33(3/0/1) 34(3/0/1) ,B],I,d 29(3/0/1) 31(3/0/1) 32(3/0/1) 33(3/0/1) 35(3/0/1) 36(3/0/1) ,B],I,d 29(3/0/1) 31(3/0/1) 32(3/0/1) 33(3/0/1) 35(3/0/1) 36(3/0/1) 8-22 M68020 USER’S MANUAL MOTOROLA...
  • Page 238 18(2/0/0) 19(2/0/1) 19(2/0/1) 19(2/0/1) 19(2/0/1) 19(2/0/1) 21(2/0/1) ,B],I) 20(2/0/0) 20(2/0/0) 21(2/0/1) 21(2/0/1) 21(2/0/1) 21(2/0/1) 21(2/0/1) 23(2/0/1) ,B],I,d 22(2/0/0) 22(2/0/0) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 25(2/0/1) ,B],I,d 22(2/0/0) 22(2/0/0) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 25(2/0/1) MOTOROLA M68020 USER’S MANUAL 8- 23...
  • Page 239 21(2/0/1) 23(2/0/1) 22(2/0/1) 24(2/0/1) 28(2/0/1) 26(3/0/1) 28(3/0/1) 29(3/0/1) ,B],I) 23(2/0/1) 25(2/0/1) 24(2/0/1) 26(2/0/1) 30(2/0/1) 28(3/0/1) 30(3/0/1) 31(3/0/1) ,B],I,d 25(2/0/1) 27(2/0/1) 26(2/0/1) 28(2/0/1) 32(2/0/1) 30(3/0/1) 32(3/0/1) 33(3/0/1) ,B],I,d 25(2/0/1) 27(2/0/1) 26(2/0/1) 28(2/0/1) 32(2/0/1) 30(3/0/1) 32(3/0/1) 33(3/0/1) 8-24 M68020 USER’S MANUAL MOTOROLA...
  • Page 240 28(3/0/1) 30(3/0/1) 31(3/0/1) 32(3/0/1) 34(3/0/1) 35(3/0/1) ,B],I,d 28(3/0/1) 30(3/0/1) 31(3/0/1) 32(3/0/1) 34(3/0/1) 35(3/0/1) ,B],I) 30(3/0/1) 32(3/0/1) 33(3/0/1) 34(3/0/1) 36(3/0/1) 37(3/0/1) ,B],I,d 32(3/0/1) 34(3/0/1) 35(3/0/1) 36(3/0/1) 38(3/0/1) 39(3/0/1) ,B],I,d 32(3/0/1) 34(3/0/1) 35(3/0/1) 36(3/0/1) 38(3/0/1) 39(3/0/1) MOTOROLA M68020 USER’S MANUAL 8- 25...
  • Page 241 23(2/3/0) 23(2/3/0) 25(2/3/1) 25(2/3/1) 25(2/3/1) 27(2/3/1) 27(2/3/1) 29(2/4/1) ,B],I) 23(2/3/0) 23(2/3/0) 25(2/3/1) 25(2/3/1) 25(2/3/1) 27(2/3/1) 27(2/3/1) 29(2/4/1) ,B],I,d 25(2/3/0) 25(2/3/0) 27(2/3/1) 27(2/3/1) 27(2/3/1) 29(2/3/1) 29(2/3/1) 31(2/4/1) ,B],I,d 27(2/4/0) 27(2/4/0) 29(2/4/1) 29(2/4/1) 29(2/4/1) 31(2/4/1) 31(2/4/1) 33(2/5/1) 8-26 M68020 USER’S MANUAL MOTOROLA...
  • Page 242 30(2/4/1) 28(2/3/1) 32(2/4/1) 37(2/4/1) 28(3/3/1) 35(3/4/1) 38(3/4/1) ,B],I) 27(2/3/1) 30(2/4/1) 28(2/3/1) 32(2/4/1) 37(2/4/1) 28(3/3/1) 35(3/4/1) 38(3/4/1) ,B],I,d 29(2/3/1) 32(2/4/1) 30(2/3/1) 34(2/4/1) 39(2/4/1) 30(3/3/1) 37(3/4/1) 40(3/4/1) ,B],I,d 31(2/4/1) 34(2/5/1) 32(2/4/1) 36(2/5/1) 41(2/5/1) 32(3/4/1) 39(3/5/1) 42(3/5/1) MOTOROLA M68020 USER’S MANUAL 8- 27...
  • Page 243 ,B],I,d 34(3/4/1) 37(3/4/1) 40(3/5/1) 41(3/4/1) 42(3/5/1) 44(3/5/1) ,B],I,d 35(3/4/1) 38(3/4/1) 41(3/5/1) 42(3/4/1) 43(3/5/1) 45(3/5/1) ,B],I) 35(3/4/1) 38(3/4/1) 41(3/5/1) 42(3/4/1) 43(3/5/1) 45(3/5/1) ,B],I,d 37(3/4/1) 40(3/4/1) 43(3/5/1) 44(3/4/1) 45(3/5/1) 47(3/5/1) ,B],I,d 39(3/5/1) 42(3/5/1) 45(3/6/1) 46(3/5/1) 47(3/6/1) 49(3/6/1) 8-28 M68020 USER’S MANUAL MOTOROLA...
  • Page 244: Special-Purpose Move Instruction

    5(0/0/1) 5(0/0/1) 7(0/1/1) MOVE 0(0/0/0) 2(0/0/0) 3(0/1/0) SWAP Rx,Ry 1(0/0/0) 4(0/0/0) 4(0/1/0) n—Number of Registers to Transfer RL—Register List Add Fetch Effective Address Time †Add Calculate Effective Address Time ‡Add Calculate Immediate Address Time MOTOROLA M68020 USER’S MANUAL 8- 29...
  • Page 245: Arithmetic/Logical Instructions

    MUL.L EA,Dn 41(0/0/0) 43(0/0/0) 44(0/1/0) DIVU.W EA,Dn 42(0/0/0) 44(0/0/0) 44(0/1/0) DIVU.L EA,Dn 76(0/0/0) 78(0/0/0) 79(0/1/0) DIVS.W EA,Dn 54(0/0/0) 56(0/0/0) 57(0/1/0) DIVS.L EA,Dn 88(0/0/0) 90(0/0/0) 91(0/1/0) Add Fetch Effective Address Time Add Fetch Immediate Address Time 8-30 M68020 USER’S MANUAL MOTOROLA...
  • Page 246: Immediate Arithmetic/Logical Instructions

    3(0/1/0) #<data >,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1) SUBI #<data >,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0) SUBI #<data >,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1) CMPI #<data >,EA 0(0/0/0) 2(0/0/0) 3(0/1/0) Add Fetch Effective Address Time Add Fetch Immediate Address Time MOTOROLA M68020 USER’S MANUAL 8- 31...
  • Page 247: Binary-Coded Decimal Operations

    3(0/1/0) SUBX –(An),–(An) 10(2/0/1) 12(2/0/1) 13(2/1/1) CMPM (An)+,(An)+ 8(2/0/0) 9(2/0/0) 10(2/1/0) PACK Dn,Dn,#<data > 3(0/0/0) 6(0/0/0) 7(0/1/0) PACK –(An),–(An),#<data > 11(1/0/1) 13(1/0/1) 13(1/1/1) UNPK Dn,Dn,#<data > 5(0/0/0) 8(0/0/0) 9(0/1/0) UNPK –(An),–(An),#<data > 11(1/0/1) 13(1/0/1) 13(1/1/1) 8-32 M68020 USER’S MANUAL MOTOROLA...
  • Page 248: Single-Operand Instructions

    1(0/0/0) 4(0/0/0) 4(0/1/0) NBCD 6(0/0/0) 6(0/0/0) 6(0/1/0) 1(0/0/0) 4(0/0/0) 4(0/1/0) † 6(0/0/1) 6(0/0/1) 6(0/1/1) 1(0/0/0) 4(0/0/0) 4(0/1/0) † 12(1/0/1) 12(1/0/1) 13(1/1/1) 0(0/0/0) 2(0/0/0) 3(0/1/0) Add Fetch Effective Address Time †Add Calculate Effective Address Time MOTOROLA M68020 USER’S MANUAL 8- 33...
  • Page 249: Shift/Rotate Instructions

    7(0/0/1) 7(0/0/1) 7(0/1/1) Mem by 1 7(0/0/1) 7(0/0/1) 7(0/1/1) ROXL 9(0/0/0) 12(0/0/0) 12(0/1/0) ROXR 9(0/0/0) 12(0/0/0) 12(0/1/0) ROXd Mem by 1 5(0/0/1) 5(0/0/1) 6(0/1/1) Add Fetch Effective Address Time d—Direction of Shift/Rotate, L or R 8-34 M68020 USER’S MANUAL MOTOROLA...
  • Page 250: Bit Manipulation Instructions

    4(0/0/1) 5(0/1/1) BSET #<data >,Dn 1(0/0/0) 4(0/0/0) 5(0/1/0) BSET Dn,Dn 1(0/0/0) 4(0/0/0) 5(0/1/0) BSET #<data >,Mem 4(0/0/1) 4(0/0/1) 5(0/1/1) BSET Dn,Mem 4(0/0/1) 4(0/0/1) 5(0/1/1) Add Fetch Effective Address Time Add Fetch Immediate Address Time MOTOROLA M68020 USER’S MANUAL 8- 35...
  • Page 251: Bit Field Manipulation Instructions

    ‡Add Calculate Immediate Address Time NOTE: A bit field of 32 bits may span five bytes that require two operand cycles to access or may span four bytes that require only one operand cycle to access. 8-36 M68020 USER’S MANUAL MOTOROLA...
  • Page 252: Conditional Branch Instructions

    6(0/0/0) 7(0/1/0) Bcc.L (Not Taken) 3(0/0/0) 6(0/0/0) 9(0/2/0) DBcc (cc = False, Count Not Expired) 3(0/0/0) 6(0/0/0) 9(0/2/0) DBcc (cc = False, Count Expired) 7(0/0/0) 10(0/0/0) 10(0/3/0) DBcc (cc = True) 3(0/0/0) 6(0/0/0) 7(0/1/0) MOTOROLA M68020 USER’S MANUAL 8- 37...
  • Page 253: Control Instructions

    12(1/2/0) UNLK 5(1/0/0) 6(1/0/0) 7(1/1/0) n—Number of Operand Transfers Required %—Add Jump Effective Address Time Add Fetch Effective Address Time Add Fetch Immediate Address Time †Add Calculate Effective Address Time ‡Add Calculate Immediate Address Time 8-38 M68020 USER’S MANUAL MOTOROLA...
  • Page 254: Exception-Related Instructions

    5(0/1/0) TRAPcc.W (Trap) 23(1/0/5) 25(1/0/5) 33(1/3/5) TRAPcc.W (No Trap) 3(0/0/0) 6(0/0/0) 7(0/1/0) TRAPcc.L (Trap) 23(1/0/5) 25(1/0/5) 33(1/3/5) TRAPcc.L (No Trap) 5(0/0/0) 8(0/0/0) 10(0/2/0) TRAPV (Trap) 23(1/0/5) 25(1/0/5) 32(1/2/5) TRAPV (No Trap) 1(0/0/0) 4(0/0/0) 5(0/1/0) MOTOROLA M68020 USER’S MANUAL 8- 39...
  • Page 255: Save And Restore Operations

    RTE (Six Word) 20(4/0/0) 21(4/0/0) 24(4/2/0) RTE (Throwaway) 15(4/0/0) 16(4/0/0) 39(4/0/0) RTE (Coprocessor) 31(7/0/0) 32(7/0/0) 33(7/1/0) RTE (Short Fault) 42(10/0/0) 43(10/0/0) 45(10/2/0) RTE (Long Fault) 91(24/0/0) 92(24/0/0) 94(24/2/0) Add the time for RTE on second stack frame. 8-40 M68020 USER’S MANUAL MOTOROLA...
  • Page 256: Applications Information

    80-bit extended-precision real data format. The interface of the MC68020/EC020 to the MC68881 or MC68882 is easily tailored to system cost/performance needs. The MC68020/EC020 and the MC68881/MC68882 communicate via standard asynchronous M68000 bus cycles.
  • Page 257: Bit Data Bus Coprocessor Connection

    Figure 9-1. 32-Bit Data Bus Coprocessor Connection The chip select ( CS ) decode circuitry is asynchronous logic that detects when a particular floating-point coprocessor is addressed. The MC68020/EC020 signals used by the logic include FC2–FC0 and A19–A13. Refer to Section 7 Coprocessor Interface Description for more information concerning the encoding of these signals.
  • Page 258: Chip Select Generation Pal

    The major concern of a system designer is to design a CS interface that meets the AC electrical specifications for both the MC68020/EC020 (MPU) and the MC68881/MC68882 (FPCP) without adding unnecessary wait states to FPCP accesses. The following maximum specifications (relative to CLK low) meet these objectives: low to AS low ≤...
  • Page 259: Chip Select Pal Equations

    PAL16L8 FPCP CS GENERATION CIRCUITRY FOR 25 MHz OPERATION MOTOROLA INC., AUSTIN, TEXAS INPUTS: OUTPUTS: CLKD !~CS = FC2 *FC1 *FC0 ;cpu space = $7 *!A19 *!A18 *A17 *!A16 ;coprocessor access = $2 *!A15 *!A14 *A13 ;coprocessor id = $1 *!CLK ;qualified by MPU clock low...
  • Page 260: Byte Select Logic For The Mc68020/Ec020

    8-, 16-, or 32-bit data port, regardless of alignment. This feature allows the programmer to write code that is not bus-width specific. When accessed, the peripheral or memory subsystem reports its actual port size to the controller, and the MC68020/EC020 then dynamically sizes the data transfer accordingly, using multiple bus cycles when necessary.
  • Page 261: Data Bus Activity For Byte, Word, And Long-Word Ports

    To satisfy this requirement, the R/ W signal must be included in the byte select logic for the MC68020/EC020. Figure 9-5 shows a block diagram of an MC68020/EC020 system with a single memory bank. The PAL provides memory-mapped byte select signals for an asynchronous 32-bit port and unmapped byte select signals for other memory banks or ports.
  • Page 262: Example Mc68020/Ec020 Byte Select Pal System Configuration

    LMDB UMDB A21–A18 MC74F32 UUDB MC74F32 MC74F32 MC74F32 A31–A2 D31–D0 32-BIT PORT A31–A2 MCM60256A MCM60256A MCM60256A MCM60256A D7–D0 D15–D8 D23–D16 D31–D24 For the MC68EC020, A23–A2. Figure 9-5. Example MC68020/EC020 Byte Select PAL System Configuration MOTOROLA M68020 USER’S MANUAL 9- 7...
  • Page 263: Mc68020/Ec020 Byte Select Pal Equations

    PAL16L8 BYTE_SELECT MC68020/EC020 BYTE DATA SELECT GENERATION FOR 32-BIT PORTS, MAPPED AND UNMAPPED. MOTOROLA INC., AUSTIN, TEXAS INPUTS: SIZ0 SIZ1 ~CPU OUTPUTS: ~UUDA ~UMDA ~LMDA ~LLDA ~UUDA ~UMDB ~LMDB ~LLDB !~UUDA = RW ;enable upper byte on read of 32-bit port +!A0 *!A1 ;directly addressed, any size...
  • Page 264: Power And Ground Considerations

    Motorola recommends using a capacitor in the range of 0.01 µF to 0.1 µF on each V pin on each device to provide filtering for most frequencies prevalent in a digital system. In addition to the individual decoupling, several bulk decoupling capacitors should be placed onto the printed circuit board with typical values in the range of 33 µF to 330 µF.
  • Page 265: Clock Driver

    9.4 CLOCK DRIVER The MC68020/EC020 is designed to sustain high performance while using low-cost memory subsystems. The MC68020/EC020 requires a stable clock source that is free of ringing and ground bounce, has sufficient rise and fall times, and meets the minimum and maximum high and low cycle times.
  • Page 266: Memory Interface

    Figure 9-8. Alternate Clock Solution 9.5 MEMORY INTERFACE The MC68020/EC020 is capable of running an external bus cycle in a minimum of three clocks (refer to Section 5 Bus Operation). The MC68020/EC020 runs an asynchronous bus cycle, terminated by the DSACK1/DSACK0 signals, and has a minimum duration of three controller clock periods in which up to four bytes (32 bits) are transferred.
  • Page 267: Access Time Calculations

    The timing paths that are critical in any memory interface are illustrated and defined in Figure 9-9. The type of device that is interfaced to the MC68020/EC020 determines exactly which of the paths is most critical. The address-to-data paths are typically the critical paths for static devices since there is no penalty for initiating a cycle to these devices and later validating that access with the appropriate bus control signal.
  • Page 268: Access Time Computation Diagram

    Figure 9-9. Access Time Computation Diagram MOTOROLA M68020 USER’S MANUAL 9- 13...
  • Page 269: Memory Access Time Equations At 16.67 And 25 Mhz

    (both numbers vary with the actual clock frequency). However, many local memory systems do not operate in a truly asynchronous manner because either the memory control logic can be related to the MC68020/EC020 clock or worst-case propagation delays are known; thus, asynchronous setup times for the DSACK1 / DSACK0 signals can be guaranteed.
  • Page 270: Module Support

    Another way to optimize the CPU-to-memory access times in a system is to use a clock frequency less than the rated maximum of the specific MC68020/EC020 device. Table 9-5 provides calculated t (see Equation 9-7 of Table 9-4) results for a 16 MHz A V D V MC68020/EC020 and a 25 MHz MC68020/EC020 operating at various clock frequencies.
  • Page 271 The opt field specifies how arguments are to be passed to the called module; the MC68020/EC020 recognizes only the options of 000 and 100; all others cause a format exception. The 000 option indicates that the called module expects to find arguments from the calling module on the stack just below the module stack frame.
  • Page 272: Module Stack Frame

    TYPE SAVED ACCESS LEVEL CONDITION CODES ARGUMENT COUNT (RESERVED) +$08 MODULE DESCRIPTION POINTER +$0C SAVED PROGRAM COUNTER +$10 SAVED MODULE DATA AREA POINTER +$18 ARGUMENTS (OPTIONAL) Figure 9-12. Module Call Stack Frame MOTOROLA M68020 USER’S MANUAL 9- 17...
  • Page 273: Access Levels

    9.8 ACCESS LEVELS The MC68020/EC020 module mechanism supports a finer level of access control beyond the distinction between user and supervisor privilege levels. The module mechanism allows a module with limited access rights to call a module with greater access rights. With...
  • Page 274: Module Call

    If opt is equal to 000 (arguments passed on the stack) in the module descriptor, the MC68020/EC020 does not save the stack pointer or load a new stack pointer value. The processor uses the module entry word to save and load the module data area pointer register and then begins execution of the called module.
  • Page 275: Module Return

    If the called module does not wish the saved module data pointer to be loaded into a register, the RTM instruction word can select register A7, and the loaded value will be overwritten with the correct stack pointer value after the module stack frame is deallocated. 9-20 M68020 USER’S MANUAL MOTOROLA...
  • Page 276: Electrical Characteristics

    This section provides the thermal characteristics and electrical specifications for the MC68020/EC020. Note that the thermal and DC electrical characteristics are listed separately for the MC68020 and the MC68EC020. All other data applies to both the MC68020 and the MC68EC020 unless otherwise noted.
  • Page 277: Mc68020 Thermal Characteristics And Dc Electrical Characteristics

    10.2.1 MC68020 Thermal Characteristics and DC Electrical Characteristics MC68020 Thermal Resistance (°C/W) The following table provides thermal resistance characteristics for junction to ambient and junction to case for the MC68020 packages with natural convection and no heatsink. θ θ Characteristic—Natural Convection and No Heatsink...
  • Page 278 (°C)—No Heatsink Values for thermal resistance presented in this document were derived using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX Microcomponent Devices,” and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup.
  • Page 279: Mc68Ec020 Thermal Characteristics And Dc Electrical Characteristics

    MC68020 DC Electrical Characteristics ± 5%; GND = 0 V = 5.0 V ; T emperature within defined ranges) Characteristics Symbol Unit Input High Voltage Input Low Voltage –0.5 µA BERR , BR , BGACK , CLK, IPL2 – IPL0 , Input Leakage Current GND ≤...
  • Page 280: Ac Electrical Characteristics

    The measurement of the AC specifications is defined by the waveforms shown in Figure 10-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in Figure 10-1. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in Figure 10-1.
  • Page 281: Drive Levels And Test Points For Ac Specifications

    Figure 10-1. Drive Levels and Test Points for AC Specifications 10-6 M68020 USER’S MANUAL MOTOROLA...
  • Page 282: Clock Input Timing Diagram

    — — — — These specifications represent an improvement over previously published specifications for the 25-MHz MC68020 and are valid only for products bearing date codes of 8827 and later. Figure 10-2. Clock Input Timing Diagram MOTOROLA M68020 USER’S MANUAL...
  • Page 283 — — — Data-In Valid to Clock Low (Setup) (Read) — — — — Late BERR/HALT Asserted to Clock Low — — — — (Setup) AS, DS Negated to DSACK≈, BERR, HALT , AVEC Negated 10-8 M68020 USER’S MANUAL MOTOROLA...
  • Page 284 — Clks This specification does not apply to the MC68EC020. These specifications represent an improvement over previously published specifications for the 25-MHz MC68020 and are valid only for product bearing date codes of 8827 and later. MOTOROLA M68020 USER’S MANUAL...
  • Page 285 10. These specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus when the MC68020/EC020 regains control of the bus after an arbitration sequence. 11. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS (allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement (specification 8B of MC68881UM/AD, MC68881/MC68882 Floating-Point Coprocessor User's Manual) .
  • Page 286: Read Cycle Timing Diagram

    Figure 10-3. Read Cycle Timing Diagram MOTOROLA M68020 USER’S MANUAL 10-11...
  • Page 287: Write Cycle Timing Diagram

    Figure 10-4. Write Cycle Timing Diagram 10-12 M68020 USER’S MANUAL MOTOROLA...
  • Page 288: Bus Arbitration Timing Diagram

    Figure 10-5. Bus Arbitration Timing Diagram MOTOROLA M68020 USER’S MANUAL 10-13...
  • Page 289: Ordering Information And Mechanical Data

    SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA This section contains the pin assignments and package dimensions of the MC68020 and the MC68EC020. In addition, detailed information is provided to be used as a guide when ordering. 11.1 STANDARD ORDERING INFORMATION 11.1.1 Standard MC68020 Ordering Information...
  • Page 290: Pin Assignments And Package Dimensions

    11.2 PIN ASSIGNMENTS AND PACKAGE DIMENSIONS 11.2.1 MC68020 RC and RP Suffix—Pin Assignment D31 D28 D25 D22 D20 D17 GND D14 D12 D9 DS D29 D26 D24 D21 D18 D16 D13 D10 D6 AS R/W D30 D27 D23 D19 GND D15 D11 D7 GND D3...
  • Page 291: Mc68020 Rc Suffix-Package Dimensions

    11.2.2 MC68020 RC Suffix—Package Dimensions RC SUFFIX CASE 791-01 MC68020 1 2 3 4 5 6 7 8 9 10 11 12 13 φ NOTES: MILLIMETERS INCHES 1. A AND B ARE DATUMS AND T IS A DATUM SURFACE. 2. POSITIONAL TOLERANCE FOR LEADS (114 PLACES).
  • Page 292: Mc68020 Rp Suffix-Package Dimensions

    11.2.3 MC68020 RP Suffix—Package Dimensions RP SUFFIX CASE 789E-02 MC68020 1 2 3 4 5 6 7 8 9 10 11 12 13 114 PL φ 0.76 (0.030) M T A S φ 0.25 (0.010) 0.17 (0.007) NOTES: MILLIMETERS INCHES 1.
  • Page 293: Mc68020 Fc And Fe Suffix-Pin Assignment

    It is recommended that all pins be connected to power and ground as indicated. NC pins are reserved by Motorola for future use and should have no external connection.
  • Page 294: Mc68020 Fc Suffix-Package Dimensions

    11.2.5 MC68020 FC Suffix—Package Dimensions FC SUFFIX CASE 831A-01 MC68020 0.25 (0.010) 0.05 (0.002) 0.20 (0.008) PIN 1 INDE 0.20 (0.008) 0.25 (0.010) 0.05. (0.002) .10 (0.004) SEATING PLANE 132 PL 0.20 (0.008) SECTION P-P NOTES: MILLIMETERS INCHES 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
  • Page 295: Mc68020 Fe Suffix-Package Dimensions

    11.2.6 MC68020 FE Suffix—Package Dimensions FE SUFFIX CASE 831-01 MC68020 0.20 (0.008) — Y 0.51 (0.020) — Y PIN 1 INDENT 0.51 (0.020) — Y 0.20 (0.008) — Y ∩ 0.10 (0.004) SEATING PLANE 132 PL 0.20 (0.008) — Y...
  • Page 296: Mc68Ec020 Rp Suffix-Pin Assignment

    It is recommended that all pins be connected to power and ground as indicated. Group V CC Address Bus B7, C7 A1, A7, C8, D13 Data Bus K12, M9, N9 J13, L8, M1, M8 Logic D1, D2, E12, E13 F11, F12, J1, J2 Clock — 13-8 MC68838 USER’S MANUAL MOTOROLA...
  • Page 297: Mc68Ec020 Rp Suffix-Package Dimensions

    3. DIMENSION D INCLUDES LEAD FINISH. 34.04 35.05 1.340 1.380 2.92 3.18 0.115 0.135 0.44 0.55 0.017 0.022 2.54 BSC 0.100 BSC 3.55 0.120 0.140 3.05 1.02 1.52 0.040 0.060 4.32 4.83 0.170 0.190 30.48 BSC 1.200 BSC MOTOROLA MC68838 USER’S MANUAL 13-9...
  • Page 298: Mc68Ec020 Fg Suffix-Pin Assignment

    It is recommended that all pins be connected to power and ground as indicated. NC pins are reserved by Motorola for future use and should have no external connection.
  • Page 299: Mc68Ec020 Fg Suffix-Package Dimensions

    LOCATED ON THE LOWER RADIUS OR THE FOOT. 0.325 BSC 0.013 BSC ° ° ° ° 0.25 0.35 0.010 0.014 23.65 24.15 0.931 0.951 — — 0.13 0.005 ° ° — — 17.65 18.15 0.695 0.715 MOTOROLA MC68838 USER’S MANUAL 13-11...
  • Page 300: Interfacing An Mc68Ec020 To A Dma Device That

    Figure A-1 shows a method by which this can be achieved. MC68EC020 BGACK 74LS08 BGACK (DMA) (MC68EC020) 74LS04 (DMA) (DMA) 74LS04 74F74 (MC68EC020) +5 V Figure A-1. Bus Arbitration Circuit— MC68EC020 (Two-Wire) to DMA (Three-Wire) MOTOROLA M68020 USER’S MANUAL A- 1...
  • Page 301 Control Instructions, 8-38 Bus, 5-24 Coprocessor, 6-25, 7-1 Arbitration, 5-62 Classification, 7-4 Cycles, 5-1 Communication Protocol, 7-4 Master, 5-1 Conditional Instruction Category, 7-10 Operation, 5-1, 5-24 Coprocessor Context Restore Instruction Bus Arbitration (MC68020), 5-63 Category, 7-22 MOTOROLA M68020 USER’S MANUAL INDEX-1...
  • Page 302 MC68020, 10-4 Instruction, 6-25, 7-3 MC68EC020, 10-5 Instruction Execution, 7-6 Destination Function Code Register (DFC), 1-7 Coprocessor Detected Differences between MC68020 and MC68EC020, Data-Processing-Related Exceptions, 7-51 1-1, 5-62 Exception, 7-49 Double Bus F ault, 5-60 Format Errors, 7-52 DS Signal, 3-4, 5-4, 5-21...
  • Page 303 Interrupt Acknowledge Cycle, 5-46 cpTRAPcc, 7-15, 7-55 Long-Word Read Cycle, 5-26 Exception-Related, 8-39 MC68EC020 Bus A rbitration, 5-70 Illegal Instruction, 6-7 MC68020 Bus A rbitration, 5-63 MOVE, 8-20 Read-Modify-Write Cycle, 5-39 MOVE SR, 8-3 Reset Exception, 6-4 MOVEA, 8-20 Write Cycle, 5-33...
  • Page 304 — L — — P — Long-Word Operand, 5-10, 5-14 Package Dimensions Long-Word Read C ycle, 5-26 MC68020 FC Suffix, 11-6 Long-Word Write Cycle, 5-33 MC68020 FE Suffix, 11-7 MC68020 RC Suffix, 11-3 — M — MC68020 RP Suffix, 11-4...
  • Page 305 RMC Signal, 3-4, 5-3, 5-39 Source Function Code Register (SFC), 1-7 RTE Instruction, 6-19, 6-24 Special-Purpose MOVE Instruction, 8-29 RTM Instruction, 9-14, 9-16, 9-19 Special Status Word (SSW), 6-21 R/ W Signal, 3-4, 5-2, 5-3, 9-5 Spurious Interrupt, 5-48 MOTOROLA M68020 USER’S MANUAL INDEX-5...
  • Page 306 TAS Instruction, 5-39 — V — Thermal Characteristics, 10-1 Connections, 3-7, 9-9 MC68020, 10-2 Vector Base Register (VBR), 1-7, 2-5, 6-2 MC68020 CQFP Package, 10-2 Virtual Machine, 1-12 MC68EC020, 10-4 Virtual Memory, 1-10 MC68EC020 PQFP Package, 10-4 Thermal Resistance, 10-2, 10-4 —...

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