Motorola PowerQUICC II MPC8280 Series Reference Manual page 1328

Fast Ethernet Registers
Table 36-8 describes FPSMR fields.
Table 36-8. FPSMR Ethernet Field Descriptions
Bits Name
0 HBC Heartbeat checking
0 No heartbeat checking is performed. Do not wait for a collision after transmission.
1 Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission.
TxBD[HB] is set if the heartbeat is not heard within 40 transmit serial clocks.
1 FC Force collision
0 Normal operation
1 The channel forces a collision on transmission of every transmit frame. The MPC8280 should
be configured in loopback operation when using this feature, which allows the user to test the
MPC8280 collision logic. It causes the retry limit to be exceeded for each transmit frame.
2 SBT Stop backoff timer
0 The backoff timer functions normally.
1 The backoff timer (for the random wait after a collision) is stopped whenever carrier sense is
active. In this method, the retransmission is less aggressive than the maximum allowed in the
IEEE 802.3 standard. The persistence (P_PER) feature in the parameter RAM can be used in
combination with the SBT bit (or in place of the SBT bit).
3 LPB Local protect bit.
0 Receiver is blocked when transmitter sends (default).
1 Receiver is not blocked when transmitter sends. Must set for full-duplex operation. For external
loopback, GFMR[DIAG] must be programmed also; see Section 30.2, "General FCC Mode
Registers (GFMRx)."
4 LCW Late collision window
0 A late collision is any collision that occurs at least 64 bytes from the preamble.
1 A late collision is any collision that occurs at least 56 bytes from the preamble.
5 FDE Full duplex Ethernet
0 Disable full-duplex
1 Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed.
6 MON RMON mode
0 Disable RMON mode
1 Enable RMON mode
7–8 — Reserved, should be zero
9 PRO Promiscuous
0 Check the destination address of incoming frames.
1 Receive the frame regardless of its address. A CAM can be used for address filtering when
FSMR[CAM] is set.
10 FCE Flow control enable
0 Flow control is not enabled
1 Flow control is enabled
11 RSH Receive short frames
0 Discard short frames (frames smaller than the value specified in MINFLR).
1 Receive short frames.
12–13 — Reserved, should be zero.
14 RMII RMII interface mode
0 MII interface
1 RMII interface. RMII to/from MII conversion logic is enabled.
36-22
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